slederer
4d4cc0c535
dram_bridge: cleanup
...
- mem_wait must be enabled on each write
- dcache_hit is never true on a write, so the
~dcache_hit clause was always true
2025-09-30 00:49:17 +02:00
slederer
2735b80fec
tdraudio: remove unneeded status flags, tweak project settings
2025-09-29 20:40:07 +02:00
slederer
12033bb6d2
tdraudio: add direct amplitude control
2025-09-29 19:10:48 +02:00
slederer
57430a4df6
tdraudio: add noise generator
2025-09-28 02:21:58 +02:00
slederer
2342683836
tdraudio: implement four channels
2025-09-27 01:34:17 +02:00
slederer
c354bb8cb8
tdraudio: implement multiple channels
2025-09-26 01:36:26 +02:00
slederer
a73fad5786
tdraudio: implement ΔΣ-DAC and volume control
2025-09-25 00:14:00 +02:00
slederer
d5888861d3
tdraudio: first step of implementing a sound generator
2025-09-23 23:39:04 +02:00
slederer
4e044ad2a4
sdcardlib: use slightly faster spi clock
...
also:
- new benchmark results
- experiment with synthesis settings
2025-09-16 21:57:53 +02:00
slederer
278f90a464
tridoracpu: implement data cache
2025-09-15 23:02:22 +02:00
slederer
d2cae9480c
mem: make SRAM size configurable
2025-09-09 00:13:56 +02:00
slederer
0ea7dcef29
improve Makefile, update example pictures
2025-08-15 23:55:48 +02:00
slederer
ecff04a7a0
vga framebuffer: use 640x480@60Hz video timings
...
- we still can only display 400 lines, so 80 blank lines
are added at the bottom
- we get square pixels this way and are hopefully more
compatible with monitors and other devices like
scan converters and capture cards
2025-06-22 00:33:02 +02:00
slederer
de889ef824
tridoracpu: update project file
...
- Vivado likes to do more ore less random changes
and uses absolute paths without reason :(
2025-05-25 00:31:20 +02:00
slederer
7cbf3afba5
tridoracpu: update MIG configuration for Vivado 2024
2025-05-24 23:25:57 +02:00
slederer
a060b65bb9
Merge branch 'inscache' of ssh://forgejo@git.insignificance.de:42122/slederer/Tridora-CPU.git
...
# Conflicts:
# examples/benchmarks.results.text
2025-04-13 23:21:38 +02:00
slederer
8abd9fc126
tridoracpu: cache bug fixes
2025-03-29 01:29:16 +01:00
slederer
b6bd487b7e
tridoracpu: first attempt at instruction cache
2025-03-16 00:10:53 +01:00
slederer
c2d7c6627a
tridoracpu: reduce clock speed, fix vblank flag in vgafb
2025-03-13 22:37:56 +01:00
slederer
ac42eec912
tridoracpu: add missing xci file for the DRAM controller
2025-03-09 23:51:22 +01:00
slederer
4f504c0f48
stdlib: start with valid random seed; other small changes
...
- tridoracpu: fix comment
- add benchmark some results
2025-03-09 01:57:11 +01:00
slederer
9a0aa7a431
update Vivado project file
2024-12-27 03:02:11 +01:00
slederer
a441e7e042
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
