tridoracpu: implement data cache
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slederer
parent
b2c2e8dc0c
commit
278f90a464
3 changed files with 138 additions and 38 deletions
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@ -45,6 +45,7 @@ Running benchmarks.prog
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exp() 10K 00:00:29
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cos() 10K 00:00:06
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--------------------------------------
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Arty-A7-35T
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76.92MHz, 64KB SRAM, 256MB DRAM
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running in DRAM (except corelib, stdlib, runtime)
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@ -68,7 +69,7 @@ Running benchmarks.prog
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exp() 10K 00:00:32
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cos() 10K 00:00:06
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--------------------------------------
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Arty-A7-35T
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76.92MHz, 64KB SRAM, 256MB DRAM, 16B instruction cache
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running in DRAM (except corelib, stdlib, runtime)
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@ -91,3 +92,57 @@ Running benchmarks.prog
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array copy 128k 1K 00:00:48
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exp() 10K 00:00:32
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cos() 10K 00:00:06
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--------------------------------------
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Arty-A7-35T
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76.92MHz, 64KB SRAM, 256MB DRAM,
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16B instruction cache, 16B wt data cache
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running in DRAM (except corelib, stdlib, runtime)
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Running benchmarks.prog
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empty loop 10M 00:00:07
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write variable 10M 00:00:17
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read variable 10M 00:00:20
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integer addition 10M 00:00:20
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real addition 1M 00:00:28
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integer multiplication 1M 00:01:11
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real multiplication 1M 00:00:59
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integer division 1M 00:01:36
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real division 1M 00:01:05
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string indexing 1M 00:00:39
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string iteration 1M 00:00:19
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new/dispose 1k 1M 00:00:19
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new/dispose 128k 1M 00:00:19
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array copy 1k 10K 00:00:03
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array copy 128k 1K 00:00:39
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exp() 10K 00:00:26
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cos() 10K 00:00:05
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--------------------------------------
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Arty-A7-35T
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76.92MHz, 64KB SRAM, 256MB DRAM,
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16B instruction cache, 16B wb data cache
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running in DRAM (except corelib, stdlib, runtime)
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Running benchmarks.prog
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empty loop 10M 00:00:04
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write variable 10M 00:00:11
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read variable 10M 00:00:18
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integer addition 10M 00:00:18
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real addition 1M 00:00:27
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integer multiplication 1M 00:00:49
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real multiplication 1M 00:00:58
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integer division 1M 00:01:06
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real division 1M 00:01:04
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string indexing 1M 00:00:36
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string iteration 1M 00:00:19
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new/dispose 1k 1M 00:00:18
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new/dispose 128k 1M 00:00:18
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array copy 1k 10K 00:00:03
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array copy 128k 1K 00:00:39
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exp() 10K 00:00:25
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cos() 10K 00:00:05
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@ -107,8 +107,14 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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);
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(*KEEP*) reg [DRAM_DATA_WIDTH-1:0] ins_cache;
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(*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
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(*KEEP*) wire cache_hit = mem_read_enable && mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
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(*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] icached_addr;
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(*KEEP*) wire icache_hit = mem_read_enable && mem_read_ins && (icached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
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(*KEEP*) reg [DRAM_DATA_WIDTH-1:0] d_cache;
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(*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] dcached_addr;
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(*KEEP*) wire dcache_hit = mem_read_enable && !mem_read_ins && (dcached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
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wire cache_hit = icache_hit | dcache_hit;
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reg [WIDTH-1:0] read_buf;
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reg read_inprogress = 0;
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@ -125,25 +131,32 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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wire [1:0] word_sel = mem_addr[3:2];
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wire [WIDTH-1:0] read_word =
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word_sel == 3'b11 ? app_rd_data[31:0] :
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word_sel == 3'b10 ? app_rd_data[63:32] :
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word_sel == 3'b01 ? app_rd_data[95:64] :
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word_sel == 2'b11 ? app_rd_data[31:0] :
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word_sel == 2'b10 ? app_rd_data[63:32] :
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word_sel == 2'b01 ? app_rd_data[95:64] :
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app_rd_data[127:96];
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wire [WIDTH-1:0] read_cached_word =
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word_sel == 3'b11 ? ins_cache[31:0] :
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word_sel == 3'b10 ? ins_cache[63:32] :
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word_sel == 3'b01 ? ins_cache[95:64] :
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wire [WIDTH-1:0] read_icached_word =
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word_sel == 2'b11 ? ins_cache[31:0] :
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word_sel == 2'b10 ? ins_cache[63:32] :
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word_sel == 2'b01 ? ins_cache[95:64] :
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ins_cache[127:96];
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(*KEEP*) assign mem_read_data = cache_hit ? read_cached_word :
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wire [WIDTH-1:0] read_dcached_word =
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word_sel == 2'b11 ? d_cache[31:0] :
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word_sel == 2'b10 ? d_cache[63:32] :
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word_sel == 2'b01 ? d_cache[95:64] :
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d_cache[127:96];
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(*KEEP*) assign mem_read_data = icache_hit ? read_icached_word :
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dcache_hit ? read_dcached_word :
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app_rd_data_valid ? read_word : read_buf;
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// set the write mask according to the lower bits of the address
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// (ignoring bit 0)
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assign app_wdf_mask = word_sel == 3'b11 ? 16'b1111111111110000 :
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word_sel == 3'b10 ? 16'b1111111100001111 :
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word_sel == 3'b01 ? 16'b1111000011111111 :
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assign app_wdf_mask = word_sel == 2'b11 ? 16'b1111111111110000 :
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word_sel == 2'b10 ? 16'b1111111100001111 :
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word_sel == 2'b01 ? 16'b1111000011111111 :
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16'b0000111111111111 ;
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wire write_ready = mem_write_enable & app_wdf_rdy & app_rdy;
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@ -152,7 +165,7 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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assign app_wdf_data = { {4{mem_write_data}} };
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assign mem_wait = (dram_read_enable & ~read_inprogress) |
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(mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
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(mem_write_enable & ~dcache_hit & (~app_wdf_rdy | ~app_rdy)) |
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(read_inprogress & ~app_rd_data_valid);
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assign app_en = (dram_read_enable & ~read_inprogress) |
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@ -160,25 +173,58 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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assign app_cmd = dram_read_enable ? CMD_READ : CMD_WRITE;
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/* set instruction cache */
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always @(posedge dram_front_clk)
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begin
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if(dram_read_enable && mem_read_ins && app_rd_data_valid)
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begin
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ins_cache <= app_rd_data;
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cached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
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icached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
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end
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end
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/* set data cache */
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always @(posedge dram_front_clk)
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begin
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if(dram_read_enable && !mem_read_ins && app_rd_data_valid)
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begin
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d_cache <= app_rd_data;
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dcached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
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end
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/* write-through cache - invalidate on write */
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/* invalidate data cache on write */
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// if(mem_write_enable && dcached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4])
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// dcached_addr <= {DRAM_ADDR_WIDTH-4{1'b1}};
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/* write-back cache - update cache on write */
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// write back to data cache on mem_write
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if(mem_write_enable && dcached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4])
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begin
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case(word_sel)
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2'b11: d_cache[31:0] <= mem_write_data;
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2'b10: d_cache[63:32] <= mem_write_data;
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2'b01: d_cache[95:64] <= mem_write_data;
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2'b00: d_cache[127:96] <= mem_write_data;
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endcase
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end
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end
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/* transfer read data, either from cache or from DRAM */
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always @(posedge dram_front_clk)
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begin
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if(dram_read_enable & ~read_inprogress & app_rdy)
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read_inprogress <= 1;
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if(read_inprogress & app_rd_data_valid)
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read_inprogress <= 0;
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if(dram_read_enable & app_rd_data_valid)
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read_buf <= mem_read_data;
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else
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if (mem_read_enable & cache_hit)
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read_buf <= read_cached_word;
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if (mem_read_enable & icache_hit)
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read_buf <= read_icached_word;
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else
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if (mem_read_enable & dcache_hit)
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read_buf <= read_dcached_word;
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end
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endmodule
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@ -349,15 +349,22 @@
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="22">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
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<Desc>Vivado Synthesis Defaults</Desc>
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<StratHandle Name="Flow_PerfOptimized_high" Flow="Vivado Synthesis 2024">
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<Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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<Step Id="synth_design">
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<Option Id="Directive">7</Option>
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<Option Id="FsmExtraction">1</Option>
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<Option Id="KeepEquivalentRegisters">1</Option>
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<Option Id="NoCombineLuts">1</Option>
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<Option Id="ResourceSharing">2</Option>
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<Option Id="ShregMinSize">5</Option>
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</Step>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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@ -371,26 +378,18 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
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<Desc>Best predicted directive for place_design.</Desc>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design">
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<Option Id="Directive">0</Option>
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</Step>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design">
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<Option Id="Directive">20</Option>
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</Step>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design">
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<Option Id="Directive">2</Option>
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</Step>
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<Step Id="route_design">
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<Option Id="Directive">1</Option>
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</Step>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream">
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<Option Id="BinFile">1</Option>
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