tridoracpu: cache bug fixes
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slederer
parent
651a451d53
commit
8abd9fc126
5 changed files with 27 additions and 27 deletions
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@ -106,10 +106,9 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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.sys_rst (rst_n)
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);
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reg [DRAM_DATA_WIDTH-1:0] ins_cache;
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reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
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wire cache_hit = mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH:4]);
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wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? ins_cache : app_rd_data;
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(*KEEP*) reg [DRAM_DATA_WIDTH-1:0] ins_cache;
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(*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
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(*KEEP*) wire cache_hit = mem_read_enable && mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
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reg [WIDTH-1:0] read_buf;
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reg read_inprogress = 0;
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@ -123,20 +122,22 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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// select a word from the 128 bits transferred by the dram controller
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// according to the lower bits of the address (ignoring bits 1:0)
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wire [WIDTH-1:0] read_word;
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wire [1:0] word_sel = mem_addr[3:2];
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// assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] :
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// word_sel == 3'b10 ? app_rd_data[63:32] :
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// word_sel == 3'b01 ? app_rd_data[95:64] :
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// app_rd_data[127:96];
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wire [WIDTH-1:0] read_word =
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word_sel == 3'b11 ? app_rd_data[31:0] :
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word_sel == 3'b10 ? app_rd_data[63:32] :
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word_sel == 3'b01 ? app_rd_data[95:64] :
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app_rd_data[127:96];
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assign read_word = word_sel == 3'b11 ? read_data_wrapper[31:0] :
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word_sel == 3'b10 ? read_data_wrapper[63:32] :
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word_sel == 3'b01 ? read_data_wrapper[95:64] :
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read_data_wrapper[127:96];
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wire [WIDTH-1:0] read_cached_word =
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word_sel == 3'b11 ? ins_cache[31:0] :
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word_sel == 3'b10 ? ins_cache[63:32] :
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word_sel == 3'b01 ? ins_cache[95:64] :
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ins_cache[127:96];
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assign mem_read_data = app_rd_data_valid ? read_word : read_buf;
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(*KEEP*) assign mem_read_data = cache_hit ? read_cached_word :
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app_rd_data_valid ? read_word : read_buf;
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// set the write mask according to the lower bits of the address
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// (ignoring bit 0)
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@ -161,10 +162,10 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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always @(posedge dram_front_clk)
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begin
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if(mem_read_enable && mem_read_ins && ~cache_hit && app_rd_data_valid)
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if(dram_read_enable && mem_read_ins && app_rd_data_valid)
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begin
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ins_cache <= mem_read_data;
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cached_addr <= mem_addr[DRAM_ADDR_WIDTH:4];
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ins_cache <= app_rd_data;
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cached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
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end
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end
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@ -176,5 +177,8 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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read_inprogress <= 0;
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if(dram_read_enable & app_rd_data_valid)
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read_buf <= mem_read_data;
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else
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if (mem_read_enable & cache_hit)
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read_buf <= read_cached_word;
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end
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endmodule
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@ -107,7 +107,7 @@ module sdspi(
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tx_fifo_empty
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);
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fifo #(.ADDR_WIDTH(8)) rx_fifo(clk, reset,
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fifo #(.ADDR_WIDTH(10)) rx_fifo(clk, reset,
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rx_fifo_wr_en, rx_fifo_rd_en,
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rx_shifter, rx_fifo_out,
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rx_fifo_full,
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@ -68,7 +68,7 @@ module top(
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localparam ADDR_WIDTH = 32, WIDTH = 32,
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ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
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wire [ADDR_WIDTH-1:0] mem_addr;
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(* KEEP *) wire [ADDR_WIDTH-1:0] mem_addr;
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wire [WIDTH-1:0] mem_read_data;
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wire [WIDTH-1:0] mem_write_data;
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(* KEEP *) wire mem_wait;
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@ -91,7 +91,7 @@ module top(
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wire [ADDR_WIDTH-1:0] dram_addr;
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wire [WIDTH-1:0] dram_read_data, dram_write_data;
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wire dram_read_enable, dram_write_enable, dram_wait;
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wire dram_read_ins;
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(* KEEP *) wire dram_read_ins;
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dram_bridge dram_bridge0 (dram_addr,
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dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,
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@ -361,9 +361,7 @@
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</Run>
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<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@ -399,9 +397,7 @@
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</Run>
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<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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