slederer 4f504c0f48 stdlib: start with valid random seed; other small changes ... - tridoracpu: fix comment - add benchmark some results		2025-03-09 01:57:11 +01:00
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tridoracpu.srcs	stdlib: start with valid random seed; other small changes	2025-03-09 01:57:11 +01:00
sdspi_testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
tridoracpu.xpr	update Vivado project file	2024-12-27 03:02:11 +01:00