slederer 4d4cc0c535 dram_bridge: cleanup ... - mem_wait must be enabled on each write - dcache_hit is never true on a write, so the ~dcache_hit clause was always true		2025-09-30 00:49:17 +02:00
..
tridoracpu.srcs	dram_bridge: cleanup	2025-09-30 00:49:17 +02:00
sdspi_testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
tridoracpu.xpr	tdraudio: remove unneeded status flags, tweak project settings	2025-09-29 20:40:07 +02:00