tridoracpu: reduce clock speed, fix vblank flag in vgafb
This commit is contained in:
slederer
parent
4f504c0f48
commit
c2d7c6627a
7 changed files with 76 additions and 47 deletions
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@ -216,3 +216,5 @@ set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports rst]
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#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
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set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
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set_max_delay -from [get_pins vgafb0/display_timings_inst/o_vblank_reg/C] -to [get_pins vgafb0/vblank_xfer_reg/D] 3.000
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@ -17,7 +17,9 @@ module cpu_clkgen(
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
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.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
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.CLKOUT0_DIVIDE_F(12.0), // Divide amount for CLKOUT0 (1.000-128.000).
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// CPU Clock: 12.0 = 83.33MHz CPU Clock, 333.33MHz Memory Clock
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// 13.0 = 76.92MHz CPU Clock, 307.69MHz Memory Clock
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.CLKOUT0_DIVIDE_F(13.0), // Divide amount for CLKOUT0 (1.000-128.000).
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.CLKOUT1_DIVIDE(5),
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.CLKOUT2_DIVIDE(40), // 40 = 25MHz pixel clock (should be 25.175MHz per spec) for 640x480
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//.CLKOUT2_DIVIDE(25), // 25 = 40MHz pixel clock for 800x600
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@ -39,12 +39,12 @@
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<Controller number="0">
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<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
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<TimePeriod>3000</TimePeriod>
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<TimePeriod>3300</TimePeriod>
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<VccAuxIO>1.8V</VccAuxIO>
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<PHYRatio>4:1</PHYRatio>
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<InputClkFreq>83.333</InputClkFreq>
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<InputClkFreq>75.757</InputClkFreq>
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<UIExtraClocks>0</UIExtraClocks>
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<MMCM_VCO>666</MMCM_VCO>
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<MMCM_VCO>606</MMCM_VCO>
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<MMCMClkOut0> 1.000</MMCMClkOut0>
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<MMCMClkOut1>1</MMCMClkOut1>
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<MMCMClkOut2>1</MMCMClkOut2>
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@ -39,12 +39,12 @@
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<Controller number="0">
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<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
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<TimePeriod>3000</TimePeriod>
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<TimePeriod>3250</TimePeriod>
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<VccAuxIO>1.8V</VccAuxIO>
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<PHYRatio>4:1</PHYRatio>
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<InputClkFreq>83.333</InputClkFreq>
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<InputClkFreq>76.923</InputClkFreq>
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<UIExtraClocks>0</UIExtraClocks>
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<MMCM_VCO>666</MMCM_VCO>
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<MMCM_VCO>615</MMCM_VCO>
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<MMCMClkOut0> 1.000</MMCMClkOut0>
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<MMCMClkOut1>1</MMCMClkOut1>
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<MMCMClkOut2>1</MMCMClkOut2>
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@ -3,7 +3,8 @@
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// or as clk_1hz for debugging
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`define clock cpuclk
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`define clkfreq 83333333
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//`define clkfreq 83333333
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`define clkfreq 76923076
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//`define clock clk
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//`define clkfreq 100000000
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//`define clock clk_1hz
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@ -62,10 +62,11 @@ module display_timings #(
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// o_scanline: high for one tick at the start of each visible scanline
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assign o_scanline = (o_sy >= VA_STA) && (o_sy <= VA_END) && (o_sx == H_STA);
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// set vblank at end of frame, clear at start
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always @(posedge i_pix_clk)
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begin
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if(o_frame) o_vblank <= 1;
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else if (o_de) o_vblank <= 0;
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if(o_sy == VA_END) o_vblank <= 1;
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else if (o_sy == -1) o_vblank <= 0;
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end
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always @ (posedge i_pix_clk)
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@ -175,6 +176,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
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wire scanline; // scanline start
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wire vblank; // vertical blank
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reg vblank_buf; // vertical blank in cpu clock domain
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reg vblank_xfer; // vertical blank clock domain crossing
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display_timings #( // 640x480 800x600 1280x720 1920x1080
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`ifdef RES_1024_768
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@ -233,7 +235,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
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always @(posedge pix_clk) frame_d <= frame;
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always @(posedge cpu_clk) vblank_buf <= vblank;
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always @(posedge cpu_clk) { vblank_buf, vblank_xfer } <= { vblank_xfer, vblank };
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always @(posedge cpu_clk)
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begin
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@ -1,9 +1,10 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<!-- Product Version: Vivado v2024.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="49" Path="./tridoracpu.xpr">
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<Project Product="Vivado" Version="7" Minor="67" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/>
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@ -12,20 +13,37 @@
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirIES" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="BoardPart" Val="digilentinc.com:arty-a7-35:part0:1.0"/>
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<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store"/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorVersionXsim" Val="2024.1"/>
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<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
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<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
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<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
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<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
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<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
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<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
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<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="BoardPart" Val="digilentinc.com:arty-a7-35:part0:1.1"/>
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<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
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<Option Name="ActiveSimSet" Val="sim_sdspi"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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@ -35,6 +53,8 @@
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="EnableResourceEstimation" Val="FALSE"/>
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<Option Name="SimCompileState" Val="TRUE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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@ -47,13 +67,13 @@
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="4"/>
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<Option Name="WTModelSimExportSim" Val="4"/>
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<Option Name="WTQuestaExportSim" Val="4"/>
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<Option Name="WTXSimExportSim" Val="6"/>
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<Option Name="WTModelSimExportSim" Val="6"/>
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<Option Name="WTQuestaExportSim" Val="6"/>
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<Option Name="WTIesExportSim" Val="4"/>
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<Option Name="WTVcsExportSim" Val="4"/>
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<Option Name="WTRivieraExportSim" Val="4"/>
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<Option Name="WTActivehdlExportSim" Val="4"/>
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<Option Name="WTVcsExportSim" Val="6"/>
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<Option Name="WTRivieraExportSim" Val="6"/>
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<Option Name="WTActivehdlExportSim" Val="6"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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@ -65,8 +85,10 @@
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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<Option Name="ClassicSocBoot" Val="FALSE"/>
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<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSets Version="1" Minor="32">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/cpuclk.v">
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@ -233,18 +255,6 @@
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0">
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<File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="mig_dram_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/fifo.v">
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@ -298,6 +308,18 @@
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<Option Name="xsim.simulate.runtime" Val="10ms"/>
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</Config>
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</FileSet>
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<FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0">
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<File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="mig_dram_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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@ -317,8 +339,8 @@
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<Option Name="Description" Val="Active-HDL Simulator"/>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="11">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
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<Runs Version="1" Minor="22">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design"/>
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@ -328,17 +350,17 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true">
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<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/>
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<Step Id="init_design"/>
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@ -364,9 +386,9 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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@ -377,7 +399,7 @@
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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