Tridora-CPU/tridoracpu/tridoracpu.srcs
2025-12-15 00:53:36 +01:00
..
mig_dram_0 tridoracpu: update MIG configuration for Vivado 2024 2025-05-24 23:25:57 +02:00
Arty-A7-35-Master.xdc tridoracpu: cleaned up top a bit, removed some warnings 2025-12-15 00:53:36 +01:00
bram_tdp.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
cpuclk.v tridoracpu: reduce clock speed, fix vblank flag in vgafb 2025-03-13 22:37:56 +01:00
display_clock.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
dram_bridge.v dram_bridge: cleanup 2025-09-30 00:49:17 +02:00
fifo.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
fifo_testbench.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
irqctrl.v tdraudio: remove pulse/noise waves, add sample buffer and irq 2025-10-04 00:09:10 +02:00
mem.v mem: make SRAM size configurable 2025-09-09 00:13:56 +02:00
palette.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
sdspi.v tridoracpu: cache bug fixes 2025-03-29 01:29:16 +01:00
sdspi_testbench.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
sfifo.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
stack.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
stackcpu.v tridoracpu: cleaned up top a bit, removed some warnings 2025-12-15 00:53:36 +01:00
tdraudio.v tridoracpu: cleaned up top a bit, removed some warnings 2025-12-15 00:53:36 +01:00
testbench.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
top.v tridoracpu: cleaned up top a bit, removed some warnings 2025-12-15 00:53:36 +01:00
uart.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
uart_tb.v import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
vgafb.v vga framebuffer: use 640x480@60Hz video timings 2025-06-22 00:33:02 +02:00