tridoracpu: cleaned up top a bit, removed some warnings
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slederer
parent
0016d4ea25
commit
d2f3b09e72
5 changed files with 47 additions and 58 deletions
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@ -8,8 +8,8 @@ set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
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create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
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## Switches
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set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0]
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports sw1]
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#set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0]
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#set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports sw1]
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#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
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#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
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@ -34,7 +34,7 @@ set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports led2]
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set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports led3]
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## Buttons
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set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0]
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#set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0]
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#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn1 }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
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#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
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#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
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@ -16,11 +16,11 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
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output wire write_enable,
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input wire mem_wait,
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output wire led1,
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output wire led2,
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output wire led3
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output wire debug1,
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output wire debug2,
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output wire debug3
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);
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localparam EVAL_STACK_INDEX_WIDTH = 6;
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wire reset = !rst;
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@ -90,7 +90,6 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
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wire mem_write;
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wire x_is_zero;
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// wire [WIDTH-1:0] y_plus_operand = Y + operand;
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wire x_equals_y = X == Y;
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wire y_lessthan_x = $signed(Y) < $signed(X);
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@ -105,16 +104,10 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
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assign write_enable = mem_write_enable;
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// debug output ------------------------------------------------------------------------------------
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assign led1 = reset;
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assign led2 = ins_loadc;
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assign led3 = ins_branch;
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// assign debug_out1 = { mem_read_enable, mem_write_enable, x_is_zero,
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// ins_branch, ins_aluop, y_lessthan_x, x_equals_y, {7{1'b0}}, seq_state};
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// assign debug_out2 = data_in;
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// assign debug_out3 = nX;
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// assign debug_out4 = nPC;
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// assign debug_out5 = ins;
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// assign debug_out6 = IV;
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assign debug1 = reset;
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assign debug2 = ins_loadc;
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assign debug3 = ins_branch;
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//--------------------------------------------------------------------------------------------------
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// instruction decoding
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@ -7,7 +7,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
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input wire reset,
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input wire [1:0] reg_sel,
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output wire [DATA_WIDTH-1:0] rd_data,
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input wire [DATA_WIDTH-1:0] wr_data,
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input wire [AMP_WIDTH-1:0] wr_data,
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input wire rd_en,
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input wire wr_en,
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@ -20,6 +20,9 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
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localparam TDRAU_REG_CLK = 1; /* clock divider register */
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localparam TDRAU_REG_AMP = 2; /* amplitude (volume) register */
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/* avoid warning about unconnected port */
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(* keep="soft" *) wire _unused = rd_en;
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reg channel_enable;
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reg [CLOCK_DIV_WIDTH-1:0] clock_div;
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reg [CLOCK_DIV_WIDTH-1:0] div_count;
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@ -29,12 +32,12 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
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wire fifo_wr_en;
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wire fifo_rd_en, fifo_full, fifo_empty;
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wire [DATA_WIDTH-1:0] fifo_rd_data;
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wire [AMP_WIDTH-1:0] fifo_rd_data;
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fifo #(.ADDR_WIDTH(4), .DATA_WIDTH(16)) sample_buf(
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clk, reset,
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fifo_wr_en, fifo_rd_en,
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wr_data, fifo_rd_data,
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wr_data[AMP_WIDTH-1:0], fifo_rd_data,
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fifo_full,
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fifo_empty
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);
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@ -166,9 +169,14 @@ module tdraudio #(DATA_WIDTH=32) (
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localparam AMP_BIAS = 32768;
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localparam DAC_WIDTH = 18;
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/* avoid warning about unconnected port */
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(* keep="soft" *) wire [DATA_WIDTH-1:AMP_WIDTH] _unused = wr_data[DATA_WIDTH-1:AMP_WIDTH];
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wire [4:0] chan_sel = io_addr[6:2];
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wire [1:0] reg_sel = io_addr[1:0];
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wire [AMP_WIDTH-1:0] amp_wr_data = wr_data[AMP_WIDTH-1:0];
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wire [AMP_WIDTH-1:0] chan0_amp;
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wire [DATA_WIDTH-1:0] chan0_rd_data;
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wire chan0_running;
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@ -210,25 +218,25 @@ module tdraudio #(DATA_WIDTH=32) (
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{DATA_WIDTH{1'b1}};
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wavegen chan0(clk, reset, reg_sel,
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chan0_rd_data, wr_data,
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chan0_rd_data, amp_wr_data,
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chan0_rd_en, chan0_wr_en,
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chan0_amp,
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chan0_running, chan0_irq);
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wavegen chan1(clk, reset, reg_sel,
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chan1_rd_data, wr_data,
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chan1_rd_data, amp_wr_data,
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chan1_rd_en, chan1_wr_en,
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chan1_amp,
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chan1_running, chan1_irq);
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wavegen chan2(clk, reset, reg_sel,
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chan2_rd_data, wr_data,
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chan2_rd_data, amp_wr_data,
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chan2_rd_en, chan2_wr_en,
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chan2_amp,
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chan2_irq, chan2_running);
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wavegen chan3(clk, reset, reg_sel,
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chan3_rd_data, wr_data,
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chan3_rd_data, amp_wr_data,
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chan3_rd_en, chan3_wr_en,
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chan3_amp,
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chan3_running, chan3_irq);
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@ -15,9 +15,6 @@
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module top(
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input wire clk,
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input wire rst,
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input wire btn0,
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input wire sw0,
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input wire sw1,
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output wire led0,
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output wire led1,
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output wire led2,
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@ -229,6 +226,15 @@ module top(
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assign uart_rd_data = { {WIDTH-10{1'b1}}, uart_rx_avail, uart_tx_busy, uart_rx_data };
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wire audio_irq;
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buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
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uart_baud,
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uart_txd_in, uart_rxd_out,
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uart_rx_clear, uart_tx_en,
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uart_rx_avail, uart_tx_busy,
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uart_tx_data, uart_rx_data);
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// audio controller
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`ifdef ENABLE_TDRAUDIO
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wire [WIDTH-1:0] tdraudio_wr_data;
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wire [WIDTH-1:0] tdraudio_rd_data;
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@ -273,13 +279,6 @@ module top(
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`endif
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-1;
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buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
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uart_baud,
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uart_txd_in, uart_rxd_out,
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uart_rx_clear, uart_tx_en,
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uart_rx_avail, uart_tx_busy,
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uart_tx_data, uart_rx_data);
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// CPU -----------------------------------------------------------------
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stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
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.addr(mem_addr),
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@ -287,7 +286,7 @@ module top(
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.read_ins(dram_read_ins),
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.data_out(mem_write_data), .write_enable(mem_write_enable),
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.mem_wait(mem_wait),
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.led1(led1), .led2(led2), .led3(led3));
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.debug1(led1), .debug2(led2), .debug3(led3));
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// Interrupt Controller
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irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,
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@ -356,15 +356,12 @@
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="22">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2024">
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<Desc>Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations.</Desc>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design">
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<Option Id="ControlSetOptThreshold">1</Option>
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<Option Id="Directive">1</Option>
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</Step>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
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@ -381,26 +378,18 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Uses multiple algorithms for optimization, placement, and routing to get potentially better results." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Performance_Explore" Flow="Vivado Implementation 2024">
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<Desc>Uses multiple algorithms for optimization, placement, and routing to get potentially better results.</Desc>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design">
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<Option Id="Directive">0</Option>
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</Step>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design">
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<Option Id="Directive">0</Option>
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</Step>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design">
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<Option Id="Directive">0</Option>
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</Step>
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<Step Id="route_design">
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<Option Id="Directive">0</Option>
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</Step>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream">
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<Option Id="BinFile">1</Option>
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