| .. |
|
mig_dram_0
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
Arty-A7-35-Master.xdc
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
bram_tdp.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
cpuclk.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
cpuclk_ccgm.v
|
tridoracpu: clock, mem and top variants for CCGMA1 chip
|
2025-02-27 01:41:33 +01:00 |
|
display_clock.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
dram_bridge.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
fifo.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
fifo_testbench.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
GateMateA1-EVB.ccf
|
tridoracpu: trim down pins in constraints file
|
2025-02-28 02:32:37 +01:00 |
|
irqctrl.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
mem.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
mem_ccgm.v
|
tridoracpu: clock, mem and top variants for CCGMA1 chip
|
2025-02-27 01:41:33 +01:00 |
|
palette.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
sdspi.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
sdspi_testbench.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
sfifo.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
stack.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
stackcpu.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
testbench.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
top.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
top_ccgm.v
|
tridoracpu: trim down pins in constraints file
|
2025-02-28 02:32:37 +01:00 |
|
uart.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
uart_tb.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
|
vgafb.v
|
import Vivado project, rearrange Verilog sources
|
2024-09-27 22:14:57 +02:00 |
