129 lines
3.4 KiB
Verilog
129 lines
3.4 KiB
Verilog
`timescale 1ns / 1ps
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// 32 bit wide rom with byte addressing (address bits 1-0 are ignored)
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module rom32 #(parameter ADDR_WIDTH = 11, DATA_WIDTH = 32)
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(
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input wire clk,
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input wire [ADDR_WIDTH-1:0] addr,
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output reg [DATA_WIDTH-1:0] data_out,
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input wire read_enable
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);
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 0
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reg [DATA_WIDTH-1:0] rom [0:(2**(ADDR_WIDTH-2))-1];
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initial begin
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$readmemb("rom.mem", rom);
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end
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always @(posedge clk) data_out <= rom[internal_addr];
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endmodule
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module ram32 #(parameter ADDR_WIDTH = 16, DATA_WIDTH = 32)
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(
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input wire clk,
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input wire [ADDR_WIDTH-1:0] addr,
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output reg [DATA_WIDTH-1:0] data_out,
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input wire read_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire write_enable
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);
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reg [DATA_WIDTH-1:0] ram [0:(2**(ADDR_WIDTH-2))-1]; // 32bit words with byte addressing
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 1-0
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always @(posedge clk)
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begin
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if(read_enable)
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data_out <= ram[internal_addr];
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if(write_enable)
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ram[internal_addr] <= data_in;
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end
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endmodule
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module mem #(parameter ADDR_WIDTH = 32,
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parameter DATA_WIDTH = 32)
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(
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input wire clk, rst_n,
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input wire [ADDR_WIDTH-1:0] addr,
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output wire [DATA_WIDTH-1:0] data_out,
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input wire read_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire write_enable,
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output wire io_enable,
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input wire [DATA_WIDTH-1:0] io_rd_data,
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output wire mem_wait
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);
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wire [DATA_WIDTH-1:0] ram_out, rom_out, dram_out;
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// address map:
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// ROM $0000 - $07FF 2K
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// IO $0800 - $0FFF 2K
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// RAM1 $1000 - $FFFF 60K
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wire ram_cs = addr[ADDR_WIDTH-1:12] != { {(ADDR_WIDTH-12){1'b0}}};
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wire ram1_cs = ram_cs && (addr[ADDR_WIDTH-1:16] == { {(ADDR_WIDTH-16){1'b0}}});
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wire ram2_cs = ram_cs && !ram1_cs;
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wire rom_cs = !ram_cs && addr[11] == 1'b0;
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wire io_cs = !ram_cs && addr[11] == 1'b1;
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assign io_enable = io_cs;
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wire ram_read = ram1_cs && read_enable;
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wire ram_write = ram1_cs && write_enable;
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wire rom_read = rom_cs && read_enable;
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reg [DATA_WIDTH-1:0] data_buf;
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localparam SEL_RAM1 = 0;
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localparam SEL_RAM2 = 1;
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localparam SEL_ROM = 2;
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localparam SEL_IO = 3;
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localparam SEL_ERR = 4;
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reg [1:0] out_sel;
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// test
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reg [1:0] wait_state;
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wire dram_wait = 0;
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ram32 #(.ADDR_WIDTH(16)) ram0 // 64KB RAM
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(
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.clk(clk),
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.addr(addr[15:0]),
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.data_out(ram_out),
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.read_enable(ram_read),
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.data_in(data_in),
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.write_enable(ram_write)
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);
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rom32 #(.ADDR_WIDTH(11)) rom0 // 2KB ROM
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(
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.clk(clk),
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.addr(addr[10:0]),
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.data_out(rom_out),
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.read_enable(rom_read)
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);
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assign data_out = (out_sel == SEL_RAM1 ) ? ram_out :
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(out_sel == SEL_RAM2 ) ? dram_out :
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(out_sel == SEL_ROM ) ? rom_out :
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(out_sel == SEL_IO ) ? io_rd_data :
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data_buf;
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assign mem_wait = ram2_cs && dram_wait;
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always @(posedge clk)
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begin
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data_buf <= data_out;
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if(read_enable) out_sel <=
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ram1_cs ? SEL_RAM1 :
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ram2_cs ? SEL_RAM2:
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rom_cs ? SEL_ROM :
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io_cs ? SEL_IO :
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SEL_ERR;
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end
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endmodule
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