tridoracpu: clock, mem and top variants for CCGMA1 chip
This commit is contained in:
slederer
parent
91b693979d
commit
2edd5679a1
5 changed files with 419 additions and 5 deletions
1
.gitignore
vendored
1
.gitignore
vendored
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@ -31,6 +31,7 @@ pcomp/pcomp
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pcomp/sasm
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pcomp/sdis
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tridoraemu/tridoraemu
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tridoracpu/build
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**/tridoracpu.cache/
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**/tridoracpu.hw/
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**/tridoracpu.ip_user_files/
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@ -18,19 +18,20 @@ BITSTREAM = build/$(TOP)_00.cfg.bit
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srcs = \
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$(SRCDIR)/bram_tdp.v \
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$(SRCDIR)/dram_bridge.v \
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$(SRCDIR)/fifo.v \
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$(SRCDIR)/irqctrl.v \
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$(SRCDIR)/mem.v \
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$(SRCDIR)/palette.v \
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$(SRCDIR)/sdspi.v \
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$(SRCDIR)/stackcpu.v \
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$(SRCDIR)/stack.v \
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$(SRCDIR)/top.v \
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$(SRCDIR)/uart.v \
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$(SRCDIR)/vgafb.v
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#srcs += $(SRCDIR)/ccgma1_clocks.v
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# for CCGMA1-EVB
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srcs += $(SRCDIR)/cpuclk_ccgm.v $(SRCDIR)/top_ccgm.v $(SRCDIR)/mem_ccgm.v
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# for Arty-A7
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# src += $(SRCDIR)/cpuclk.v $(SRCDIR)/top.v $(SRCDIR)/mem.v
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all: build synth impl
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clean:
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@ -49,7 +50,7 @@ $(SYNTHFILE): $(srcs)
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$(YOSYS) -ql build/synth.log -p 'read -sv $(srcs); synth_gatemate -top $(TOP) -nomx8 -vlog $(SYNTHFILE)'
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$(BITSTREAM): $(SYNTHFILE)
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$(PNR) -v -i build/$(SYNTHFILE) -o $(TOP) $(PNRFLAGS) >build/$@.log
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$(PNR) -v -i $(SYNTHFILE) -o build/$(TOP) $(PNRFLAGS) >$@.log
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prog: $(BITSTREAM)
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$(OFL) $(OFLFLAGS) --bitstream $(BITSTREAM)
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41
tridoracpu/tridoracpu.srcs/cpuclk_ccgm.v
Normal file
41
tridoracpu/tridoracpu.srcs/cpuclk_ccgm.v
Normal file
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@ -0,0 +1,41 @@
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`timescale 1ns / 1ps
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module cpu_clkgen(
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input wire rst,
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input wire clk10,
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output wire cpuclk,
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output wire locked
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);
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wire usr_pll_lock_stdy;
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wire usr_pll_lock;
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wire usr_ref_out;
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wire clk_nobuf;
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assign locked = usr_pll_lock;
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CC_PLL #(
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.REF_CLK("10.0"),
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.OUT_CLK("25.0"),
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.LOCK_REQ("1"),
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.PERF_MD("SPEED"),
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.LOW_JITTER(1),
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.CI_FILTER_CONST(2),
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.CP_FILTER_CONST(4)
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) pll_cpuclk (
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.CLK_REF(clk10),
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.CLK_FEEDBACK(1'b0),
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.USR_CLK_REF(1'b0),
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.USR_LOCKED_STDY_RST(1'b0),
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.USR_PLL_LOCKED_STDY(usr_pll_lock_stdy),
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.USR_PLL_LOCKED(usr_pll_lock),
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.CLK0(clk_nobuf),
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.CLK_REF_OUT(usr_ref_out)
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);
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CC_BUFG pll_bufg (
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.I(clk_nobuf),
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.O(cpuclk)
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);
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endmodule
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129
tridoracpu/tridoracpu.srcs/mem_ccgm.v
Normal file
129
tridoracpu/tridoracpu.srcs/mem_ccgm.v
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@ -0,0 +1,129 @@
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`timescale 1ns / 1ps
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// 32 bit wide rom with byte addressing (address bits 1-0 are ignored)
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module rom32 #(parameter ADDR_WIDTH = 11, DATA_WIDTH = 32)
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(
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input wire clk,
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input wire [ADDR_WIDTH-1:0] addr,
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output reg [DATA_WIDTH-1:0] data_out,
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input wire read_enable
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);
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 0
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reg [DATA_WIDTH-1:0] rom [0:(2**(ADDR_WIDTH-2))-1];
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initial begin
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$readmemb("rom.mem", rom);
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end
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always @(posedge clk) data_out <= rom[internal_addr];
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endmodule
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module ram32 #(parameter ADDR_WIDTH = 16, DATA_WIDTH = 32)
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(
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input wire clk,
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input wire [ADDR_WIDTH-1:0] addr,
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output reg [DATA_WIDTH-1:0] data_out,
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input wire read_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire write_enable
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);
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reg [DATA_WIDTH-1:0] ram [0:(2**(ADDR_WIDTH-2))-1]; // 32bit words with byte addressing
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 1-0
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always @(posedge clk)
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begin
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if(read_enable)
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data_out <= ram[internal_addr];
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if(write_enable)
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ram[internal_addr] <= data_in;
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end
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endmodule
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module mem #(parameter ADDR_WIDTH = 32,
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parameter DATA_WIDTH = 32)
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(
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input wire clk, rst_n,
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input wire [ADDR_WIDTH-1:0] addr,
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output wire [DATA_WIDTH-1:0] data_out,
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input wire read_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire write_enable,
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output wire io_enable,
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input wire [DATA_WIDTH-1:0] io_rd_data,
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output wire mem_wait
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);
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wire [DATA_WIDTH-1:0] ram_out, rom_out, dram_out;
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// address map:
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// ROM $0000 - $07FF 2K
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// IO $0800 - $0FFF 2K
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// RAM1 $1000 - $FFFF 60K
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wire ram_cs = addr[ADDR_WIDTH-1:12] != { {(ADDR_WIDTH-12){1'b0}}};
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wire ram1_cs = ram_cs && (addr[ADDR_WIDTH-1:16] == { {(ADDR_WIDTH-16){1'b0}}});
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wire ram2_cs = ram_cs && !ram1_cs;
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wire rom_cs = !ram_cs && addr[11] == 1'b0;
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wire io_cs = !ram_cs && addr[11] == 1'b1;
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assign io_enable = io_cs;
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wire ram_read = ram1_cs && read_enable;
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wire ram_write = ram1_cs && write_enable;
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wire rom_read = rom_cs && read_enable;
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reg [DATA_WIDTH-1:0] data_buf;
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localparam SEL_RAM1 = 0;
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localparam SEL_RAM2 = 1;
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localparam SEL_ROM = 2;
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localparam SEL_IO = 3;
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localparam SEL_ERR = 4;
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reg [1:0] out_sel;
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// test
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reg [1:0] wait_state;
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wire dram_wait = 0;
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ram32 #(.ADDR_WIDTH(16)) ram0 // 64KB RAM
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(
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.clk(clk),
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.addr(addr[15:0]),
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.data_out(ram_out),
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.read_enable(ram_read),
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.data_in(data_in),
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.write_enable(ram_write)
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);
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rom32 #(.ADDR_WIDTH(11)) rom0 // 2KB ROM
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(
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.clk(clk),
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.addr(addr[10:0]),
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.data_out(rom_out),
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.read_enable(rom_read)
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);
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assign data_out = (out_sel == SEL_RAM1 ) ? ram_out :
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(out_sel == SEL_RAM2 ) ? dram_out :
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(out_sel == SEL_ROM ) ? rom_out :
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(out_sel == SEL_IO ) ? io_rd_data :
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data_buf;
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assign mem_wait = ram2_cs && dram_wait;
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always @(posedge clk)
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begin
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data_buf <= data_out;
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if(read_enable) out_sel <=
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ram1_cs ? SEL_RAM1 :
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ram2_cs ? SEL_RAM2:
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rom_cs ? SEL_ROM :
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io_cs ? SEL_IO :
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SEL_ERR;
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end
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endmodule
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242
tridoracpu/tridoracpu.srcs/top_ccgm.v
Normal file
242
tridoracpu/tridoracpu.srcs/top_ccgm.v
Normal file
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@ -0,0 +1,242 @@
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`timescale 1ns / 1ps
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`define clock cpuclk
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`define clkfreq 25000000
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//`define clock clk
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//`define clkfreq 100000000
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//`define clock clk_1hz
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`define ENABLE_VGAFB
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`define ENABLE_MICROSD
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module top(
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input wire clk,
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input wire rst,
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output wire led0,
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input wire uart_txd_in,
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output wire uart_rxd_out
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`ifdef ENABLE_VGAFB
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,
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output wire [3:0] VGA_R,
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output wire [3:0] VGA_G,
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output wire [3:0] VGA_B,
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output wire VGA_HS_O,
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output wire VGA_VS_O
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`endif
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`ifdef ENABLE_MICROSD
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,
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output wire sd_cs_n,
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output wire sd_mosi,
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input wire sd_miso,
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output wire sd_sck,
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input wire sd_cd
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`endif
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);
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reg [31:0] counter;
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localparam ADDR_WIDTH = 32, WIDTH = 32,
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ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
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wire [ADDR_WIDTH-1:0] mem_addr;
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wire [WIDTH-1:0] mem_read_data;
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wire [WIDTH-1:0] mem_write_data;
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(* KEEP *) wire mem_wait;
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(* KEEP *) wire mem_read_enable;
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(* KEEP *) wire mem_write_enable;
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(* KEEP *) wire io_enable;
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wire [WIDTH-1:0] io_rd_data;
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wire [IOADDR_SEL-1:0] io_slot = mem_addr[IOADDR_WIDTH-1:IOADDR_WIDTH-IOADDR_SEL];
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wire irq;
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// assign led0 = mem_wait;
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wire [WIDTH-1:0] debug_data1, debug_data2,
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debug_data3, debug_data4,
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debug_data5, debug_data6;
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assign led0 = debug_data6[0];
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wire cpuclk, cpuclk_locked;
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wire dram_refclk200;
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wire pixclk = cpuclk;
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cpu_clkgen cpuclk_0(~rst, clk, cpuclk, cpuclk_locked);
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mem #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(WIDTH)) mem0(
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.clk(`clock), .rst_n(rst), .addr(mem_addr),
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.data_out(mem_read_data), .read_enable(mem_read_enable),
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.data_in(mem_write_data), .write_enable(mem_write_enable),
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.io_enable(io_enable),
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.io_rd_data(io_rd_data),
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.mem_wait(mem_wait)
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);
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`ifdef ENABLE_VGAFB
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localparam FB_ADDR_WIDTH = 14;
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wire [FB_ADDR_WIDTH-1:0] fb_rd_addr;
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wire [FB_ADDR_WIDTH-1:0] fb_wr_addr;
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wire [WIDTH-1:0] fb_rd_data;
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wire [WIDTH-1:0] fb_wr_data;
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wire fb_rd_en, fb_wr_en;
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wire fb_cs_en = io_enable && (io_slot == 2);
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assign fb_rd_en = fb_cs_en && mem_read_enable;
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assign fb_wr_en = fb_cs_en && mem_write_enable;
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assign fb_wr_data = mem_write_data;
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vgafb vgafb0(`clock, pixclk, rst,
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mem_addr[3:0], fb_rd_data, fb_wr_data,
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fb_rd_en, fb_wr_en,
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VGA_HS_O, VGA_VS_O, VGA_R, VGA_G, VGA_B);
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`endif
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// SPI SD card controller -------------------------------------------------------------------
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`ifdef ENABLE_MICROSD
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wire [7:0] spi_tx_data;
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(*KEEP*) wire [7:0] spi_rx_data;
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wire spi_tx_ready; // ready to transmit new data
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wire spi_tx_empty; // tx fifo is empty
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wire spi_rx_avail; // a byte has been received
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wire spi_rx_ovr; // receiver overrun
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wire spi_tx_write; // write strobe
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wire spi_rx_read; // read strobe (clears rx_avail)
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wire spi_card_detect; // true is card is present
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wire spi_card_changed; // card_detect signal has changed
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wire spi_card_busy; // card is busy (MISO/DO is 0)
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wire spi_ctrl_write; // set the following flags
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wire spi_rx_filter_en; // set to wait for start bit (1-to-0) when receiving
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wire spi_txrx_en; // enable transmitter and receiver
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wire spi_sclk_f_en; // enable spi clock without transceiver
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wire spi_sclk_div_wr; // set clock divider from tx_data
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wire spi_cs; // cs signal for spi controller
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wire [WIDTH-1:0] spi_rd_data;
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assign spi_cs = io_enable && (io_slot == 1);
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// spi read data: [ 0,...,0,cd,cc,cb,tr,te,ra,ro,d,d,d,d,d,d,d,d ]
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// cd = card detect, cc = card changed, cb = card busy,
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// tr = transmitter ready, te = tx fifo empty,
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// ra = received byte available, ro = receive overrun, d = received byte
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assign spi_rd_data =
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{ {WIDTH-15{1'b0}}, spi_card_detect, spi_card_changed, spi_card_busy,
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spi_tx_ready, spi_tx_empty,
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spi_rx_avail, spi_rx_ovr, spi_rx_data };
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// spi write data: [ 0,...,0,CW,CF,Cx,Cc,Cd,DR,DW,d,d,d,d,d,d,d,d ]
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// CW = control write, CF = enable receive filter, Cx = enable transceiver,
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// Cc = force spi clock on, Cd = write clock divider,
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// DR = read acknowledge, DW = data write, d = byte to be sent
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assign spi_ctrl_write = spi_cs && mem_write_enable && mem_write_data[14];
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assign spi_rx_filter_en = mem_write_data[13];
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assign spi_txrx_en = mem_write_data[12];
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assign spi_sclk_f_en = mem_write_data[11];
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assign spi_sclk_div_wr = spi_cs && mem_write_enable && mem_write_data[10];
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assign spi_rx_read = mem_write_data[9];
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assign spi_tx_write = spi_cs && mem_write_enable && mem_write_data[8];
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assign spi_tx_data = mem_write_data[7:0];
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sdspi sdspi0(.clk(`clock), .reset(~rst),
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.tx_data(spi_tx_data), .rx_data(spi_rx_data),
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.tx_ready(spi_tx_ready), .tx_empty(spi_tx_empty),
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.rx_avail(spi_rx_avail), .rx_ovr(spi_rx_ovr),
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.tx_write(spi_tx_write), .rx_read(spi_rx_read),
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.card_detect(spi_card_detect), .card_changed(spi_card_changed), .card_busy(spi_card_busy),
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// ctrl_write is used with rx_filter_en, txrx_en and spiclk_f_en
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.ctrl_write(spi_ctrl_write),
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.rx_filter_en(spi_rx_filter_en), .txrx_en(spi_txrx_en), .spiclk_f_en(spi_sclk_f_en),
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//
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.spiclk_div_wr(spi_sclk_div_wr),
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.sd_cs_n(sd_cs_n),
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.sd_mosi(sd_mosi), .sd_miso(sd_miso), .sd_sck(sd_sck), .sd_cd(sd_cd));
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`endif
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// UART -----------------------------------------------------------------------
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// uart write data: [ 0, 0, 0, 0, 0, T, C, 0, c, c, c, c, c, c, c, c ]
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// T = transmit enable, C = receiver clear, c = 8-bit-character
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// uart read data: [ 0, 0, 0, 0, 0, 0, A, B, c, c, c, c, c, c, c, c ]
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// A = char available, B = tx busy, c = 8-bit-character
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wire uart_cs = io_enable && (io_slot == 0);
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wire uart_tx_en = uart_cs && mem_write_enable && mem_write_data[10];
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wire uart_rx_clear = uart_cs && mem_write_enable && mem_write_data[9];
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wire uart_rx_avail;
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wire uart_rx_busy, uart_tx_busy;
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wire uart_err;
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wire [7:0] uart_rx_data;
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wire [7:0] uart_tx_data;
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wire [31:0] uart_baud = 32'd115200;
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wire [WIDTH-1:0] uart_rd_data;
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assign uart_tx_data = mem_write_data[7:0];
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assign uart_rd_data = { {WIDTH-10{1'b1}}, uart_rx_avail, uart_tx_busy, uart_rx_data };
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reg timer_tick;
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reg[23:0] tick_count;
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wire [1:0] irq_in = { timer_tick, uart_rx_avail };
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wire [1:0] irqc_rd_data0;
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wire [WIDTH-1:0] irqc_rd_data = { tick_count, 6'b0, irqc_rd_data0 };
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wire irqc_seten = mem_write_data[7];
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wire irqc_cs = io_enable && (io_slot == 3);
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assign io_rd_data = (io_slot == 0) ? uart_rd_data :
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`ifdef ENABLE_MICROSD
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(io_slot == 1) ? spi_rd_data :
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`endif
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`ifdef ENABLE_VGAFB
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(io_slot == 2) ? fb_rd_data :
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`endif
|
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(io_slot == 3) ? irqc_rd_data:
|
||||
|
||||
-1;
|
||||
|
||||
buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
|
||||
uart_baud,
|
||||
uart_txd_in, uart_rxd_out,
|
||||
uart_rx_clear, uart_tx_en,
|
||||
uart_rx_avail, uart_tx_busy,
|
||||
uart_tx_data, uart_rx_data);
|
||||
|
||||
// CPU -----------------------------------------------------------------
|
||||
stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
|
||||
.addr(mem_addr),
|
||||
.data_in(mem_read_data), .read_enable(mem_read_enable),
|
||||
.data_out(mem_write_data), .write_enable(mem_write_enable),
|
||||
.mem_wait(mem_wait),
|
||||
.led1(led1), .led2(led2), .led3(led3),
|
||||
.debug_out1(debug_data1),
|
||||
.debug_out2(debug_data2),
|
||||
.debug_out3(debug_data3),
|
||||
.debug_out4(debug_data4),
|
||||
.debug_out5(debug_data5),
|
||||
.debug_out6(debug_data6));
|
||||
|
||||
// Interrupt Controller
|
||||
irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,
|
||||
irqc_seten, irqc_rd_data0,
|
||||
irq);
|
||||
|
||||
// count clock ticks
|
||||
// generate interrupt every 20nth of a second
|
||||
always @ (posedge `clock)
|
||||
begin
|
||||
counter <= counter + 1;
|
||||
if (counter >= (`clkfreq/20))
|
||||
begin
|
||||
counter <= 0;
|
||||
timer_tick <= 1;
|
||||
tick_count <= tick_count + 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
timer_tick <= 0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue