179 lines
7.9 KiB
Text
179 lines
7.9 KiB
Text
#========================================================================
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# openCologne * NLnet-sponsored open-source design ware for GateMate
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#------------------------------------------------------------------------
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# Copyright (C) 2024 Chili.CHIPS*ba
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# https://opensource.org/license/bsd-3-clause
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#------------------------------------------------------------------------
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# Description:
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# Gatemate E1 evaluation board hardware pin constraints
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# file: GateMateA1-EVB.ccf
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## file: GateMateA1-EVB.ccf
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##
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## Gatemate A1-EVB Olimex board hardware pin constraints
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## #######################################################
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# Format:
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# <pin-direction> "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>;
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# Net "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>;
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#
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# Additional constraints can be appended using the pipe symbol.
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# Files are read line by line. Text after the hash symbol is ignored.
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#
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# Available pin directions:
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#
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# Pin_in
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# defines an input pin
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# Pin_out
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# defines an output pin
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# Pin_inout
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# defines a bidirectional pin
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#
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# Available pin constraints:
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#
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# SCHMITT_TRIGGER={true,false}
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# enables or disables schmitt trigger (hysteresis) option
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# PULLUP={true,false}
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# enables or disables I/O pullup resistor of nominal 50kOhm
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# PULLDOWN={true,false}
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# enables or disables I/O pulldown resistor of nominal 50kOhm
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# KEEPER={true,false}
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# enables or disables I/O keeper option
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# SLEW={slow,fast}
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# sets slew rate to slow or fast
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# DRIVE={3,6,9,12}
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# sets output drive strength to 3mA..12mA
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# DELAY_OBF={0..15}
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# adds an additional delay of n * nominal 50ps to output signal
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# DELAY_IBF={0..15}
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# adds an additional delay of n * nominal 50ps to input signal
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# FF_IBF={true,false}
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# enables or disables placing of FF in input buffer, if possible
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# FF_OBF={true,false}
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# enables or disables placing of FF in output buffer, if possible
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# LVDS_BOOST={true,false}
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# enables increased LVDS output current of 6.4mA (default: 3.2mA)
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# LVDS_TERM={true,false}
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# enables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only
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#
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# Global IO constraints can be set with the default_GPIO statement. It can be
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# overwritten by individual settings for specific GPIOs, e.g.:
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# default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten
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#========================================================================
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# GPIO Configuration - Free Bank Selectable Voltage
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# Bank Selectable VDD 1.2V/1.8V/2.5V/User PWR_Supply
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#========================================================================
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# Depending on how you turn the Olimex Board, the orientation of the pins is flipped
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# If you turn the board so that you can read the Olimex logo and the VGA Port is to the left then the upper row is GND, NA_B..
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# And the lower row is VDD_NA, NA_A... from left to right
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#
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# If you turn the board so that the VGA Port is pointing up, then the VDD_NA, NA_A pins are to the left, like on the picture of the extension below
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# This is the case for the Bank_NA1, Bank_NB1 and Bank_EB1
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#========================================================================
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# Bank NA1
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#========================================================================
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#========================================================================
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# BANK_EB1
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#========================================================================
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#========================================================================
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# BANK_MISC1
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#========================================================================
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# BANK_MISC1 is the big one to the right of the board and the configuration + text-picture below is taking into account that you have
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# the Olimex board placed so that the BANK_MISC1 is on the right side(VGA Port is on the left side).
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#========================================================================
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# Left Row
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# TOP LEFT PIN IS 2.5V
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#Net "FPGA_RESET_IN" Loc = "RST_N";
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#Net "rst_n" Loc = "IO_SB_B8";
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#Net "FPGA_LED" Loc = "IO_SB_B6"; # FPGA LED
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Net "led0" Loc = "IO_SB_B6"; # FPGA LED
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Net "rst_n" Loc = "IO_SB_B7";
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#Net "CLK0" Loc = "IO_SB_A8"; # CLK0
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Net "clk" Loc = "IO_SB_A8" | SCHMIDT_TRIGGER=true ; # CLK0
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#========================================================================
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# UART Interface
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#========================================================================
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# There is a mistake on the schematic, these need to be flipped as below
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#========================================================================
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#Net "DBG_UART_RX" Loc = "IO_SA_A6"; # GPIO12
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#Net "DBG_UART_TX" Loc = "IO_SA_B6"; # GPIO13
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Net "uart_txd_in" Loc = "IO_SA_A6"; # GPIO12
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Net "uart_rxd_out" Loc = "IO_SA_B6"; # GPIO13
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#========================================================================
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# VGA Configuration
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#========================================================================
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Net "VGA_HS_O" Loc = "IO_WB_A1";
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Net "VGA_VS_O" Loc = "IO_WB_B1";
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Net "VGA_R[3]" Loc = "IO_WB_A2";
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Net "VGA_R[2]" Loc = "IO_WB_B2";
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Net "VGA_R[1]" Loc = "IO_WB_A3";
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Net "VGA_R[0]" Loc = "IO_WB_B3";
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Net "VGA_G[3]" Loc = "IO_WB_A4";
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Net "VGA_G[2]" Loc = "IO_WB_B4";
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Net "VGA_G[1]" Loc = "IO_WB_A5";
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Net "VGA_G[0]" Loc = "IO_WB_B5";
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Net "VGA_B[3]" Loc = "IO_WB_A6";
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Net "VGA_B[2]" Loc = "IO_WB_B6";
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Net "VGA_B[1]" Loc = "IO_WB_A7";
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Net "VGA_B[0]" Loc = "IO_WB_B7";
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#========================================================================
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## PSRAM Configuration
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#========================================================================
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#Net "PSRAM_CS" Loc = "IO_WC_A4";
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#Net "PSRAM_SCLK" Loc = "IO_WC_B4";
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#Net "PSRAM_DATA[0]" Loc = "IO_WC_A5";
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#Net "PSRAM_DATA[1]" Loc = "IO_WC_B5";
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#Net "PSRAM_DATA[2]" Loc = "IO_WC_A6";
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#Net "PSRAM_DATA[3]" Loc = "IO_WC_B6";
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#Net "PSRAM_DATA[4]" Loc = "IO_WC_A7";
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#Net "PSRAM_DATA[5]" Loc = "IO_WC_B7";
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#Net "PSRAM_DATA[6]" Loc = "IO_WC_A8";
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#Net "PSRAM_DATA[7]" Loc = "IO_WC_B8";
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#========================================================================
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# PMOD
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#========================================================================
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# ___________
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#Net "PMOD_1" Loc = "IO_EA_A4"; # | 1 7 |
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#Net "PMOD_7" Loc = "IO_EA_B4"; # | 2 8 |
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#Net "PMOD_2" Loc = "IO_EA_A5"; # | 3 9 |
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#Net "PMOD_8" Loc = "IO_EA_B5"; # | 4 10 |
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#Net "PMOD_3" Loc = "IO_EA_A6"; # GND -| 5 11 | --- GND
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#Net "PMOD_9" Loc = "IO_EA_B6"; # 3-3V-| 6 12 | --- 3.3V
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#Net "PMOD_4" Loc = "IO_EA_B7"; # ___________
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#Net "PMOD_10" Loc = "IO_EA_A7";
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