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mig_dram_0
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tridoracpu: update MIG configuration for Vivado 2024
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2025-05-24 23:25:57 +02:00 |
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Arty-A7-35-Master.xdc
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tdraudio: first step of implementing a sound generator
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2025-09-23 23:39:04 +02:00 |
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bram_tdp.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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cpuclk.v
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tridoracpu: reduce clock speed, fix vblank flag in vgafb
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2025-03-13 22:37:56 +01:00 |
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display_clock.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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dram_bridge.v
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tridoracpu: implement data cache
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2025-09-15 23:02:22 +02:00 |
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fifo.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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fifo_testbench.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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irqctrl.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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mem.v
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mem: make SRAM size configurable
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2025-09-09 00:13:56 +02:00 |
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palette.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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sdspi.v
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tridoracpu: cache bug fixes
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2025-03-29 01:29:16 +01:00 |
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sdspi_testbench.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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sfifo.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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stack.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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stackcpu.v
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tridoracpu: first attempt at instruction cache
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2025-03-16 00:10:53 +01:00 |
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tdraudio.v
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tdraudio: add noise generator
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2025-09-28 02:21:58 +02:00 |
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testbench.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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top.v
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tdraudio: implement multiple channels
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2025-09-26 01:36:26 +02:00 |
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uart.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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uart_tb.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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vgafb.v
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vga framebuffer: use 640x480@60Hz video timings
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2025-06-22 00:33:02 +02:00 |
