41 lines
909 B
Verilog
41 lines
909 B
Verilog
`timescale 1ns / 1ps
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module cpu_clkgen(
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input wire rst,
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input wire clk10,
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output wire cpuclk,
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output wire locked
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);
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wire usr_pll_lock_stdy;
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wire usr_pll_lock;
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wire usr_ref_out;
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wire clk_nobuf;
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assign locked = usr_pll_lock;
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CC_PLL #(
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.REF_CLK("10.0"),
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.OUT_CLK("25.0"),
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.LOCK_REQ("1"),
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.PERF_MD("SPEED"),
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.LOW_JITTER(1),
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.CI_FILTER_CONST(2),
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.CP_FILTER_CONST(4)
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) pll_cpuclk (
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.CLK_REF(clk10),
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.CLK_FEEDBACK(1'b0),
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.USR_CLK_REF(1'b0),
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.USR_LOCKED_STDY_RST(1'b0),
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.USR_PLL_LOCKED_STDY(usr_pll_lock_stdy),
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.USR_PLL_LOCKED(usr_pll_lock),
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.CLK0(clk_nobuf),
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.CLK_REF_OUT(usr_ref_out)
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);
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CC_BUFG pll_bufg (
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.I(clk_nobuf),
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.O(cpuclk)
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);
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endmodule
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