`timescale 1ns / 1ps

module cpu_clkgen(
    input wire rst,
    input wire clk10,
    output wire cpuclk,
    output wire locked
    );

    wire usr_pll_lock_stdy;
    wire usr_pll_lock;
    wire usr_ref_out;

    wire clk_nobuf;

    assign locked = usr_pll_lock;

    CC_PLL #(
            .REF_CLK("10.0"),
            .OUT_CLK("25.0"),
            .LOCK_REQ("1"),
            .PERF_MD("SPEED"),
            .LOW_JITTER(1),
            .CI_FILTER_CONST(2),
            .CP_FILTER_CONST(4)
    ) pll_cpuclk (
            .CLK_REF(clk10),
            .CLK_FEEDBACK(1'b0),
            .USR_CLK_REF(1'b0),
            .USR_LOCKED_STDY_RST(1'b0),
            .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy),
            .USR_PLL_LOCKED(usr_pll_lock),
            .CLK0(clk_nobuf),
            .CLK_REF_OUT(usr_ref_out)
    );

    CC_BUFG pll_bufg (
            .I(clk_nobuf),
            .O(cpuclk)
    );
endmodule