slederer 2edd5679a1 tridoracpu: clock, mem and top variants for CCGMA1 chip		2025-02-27 01:41:33 +01:00
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tridoracpu.srcs	tridoracpu: clock, mem and top variants for CCGMA1 chip	2025-02-27 01:41:33 +01:00
Makefile	tridoracpu: clock, mem and top variants for CCGMA1 chip	2025-02-27 01:41:33 +01:00
sdspi_testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
tridoracpu.xpr	update Vivado project file	2024-12-27 03:02:11 +01:00