Commit graph

6 commits

Author SHA1 Message Date
slederer
8abd9fc126 tridoracpu: cache bug fixes 2025-03-29 01:29:16 +01:00
slederer
b6bd487b7e tridoracpu: first attempt at instruction cache 2025-03-16 00:10:53 +01:00
slederer
c2d7c6627a tridoracpu: reduce clock speed, fix vblank flag in vgafb 2025-03-13 22:37:56 +01:00
slederer
4f504c0f48 stdlib: start with valid random seed; other small changes
-  tridoracpu: fix comment
-  add benchmark some results
2025-03-09 01:57:11 +01:00
slederer
9a0aa7a431 update Vivado project file 2024-12-27 03:02:11 +01:00
slederer
a441e7e042 import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00