#======================================================================== 
# openCologne * NLnet-sponsored open-source design ware for GateMate
#------------------------------------------------------------------------
#                   Copyright (C) 2024 Chili.CHIPS*ba
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# 1. Redistributions of source code must retain the above copyright 
# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright 
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#              https://opensource.org/license/bsd-3-clause
#------------------------------------------------------------------------
# Description: 
# Gatemate E1 evaluation board hardware pin constraints
# file: GateMateA1-EVB.ccf
## file: GateMateA1-EVB.ccf
##
## Gatemate A1-EVB Olimex board hardware pin constraints
## #######################################################
# Format:
# <pin-direction> "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>;
# Net "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>;
#
# Additional constraints can be appended using the pipe symbol.
# Files are read line by line. Text after the hash symbol is ignored.
#
# Available pin directions:
#
# Pin_in
#   defines an input pin
# Pin_out
#   defines an output pin
# Pin_inout
#   defines a bidirectional pin
#
# Available pin constraints:
#
# SCHMITT_TRIGGER={true,false}
#   enables or disables schmitt trigger (hysteresis) option
# PULLUP={true,false}
#   enables or disables I/O pullup resistor of nominal 50kOhm
# PULLDOWN={true,false}
#   enables or disables I/O pulldown resistor of nominal 50kOhm
# KEEPER={true,false}
#   enables or disables I/O keeper option
# SLEW={slow,fast}
#   sets slew rate to slow or fast
# DRIVE={3,6,9,12}
#   sets output drive strength to 3mA..12mA
# DELAY_OBF={0..15}
#   adds an additional delay of n * nominal 50ps to output signal
# DELAY_IBF={0..15}
#   adds an additional delay of n * nominal 50ps to input signal
# FF_IBF={true,false}
#   enables or disables placing of FF in input buffer, if possible
# FF_OBF={true,false}
#   enables or disables placing of FF in output buffer, if possible
# LVDS_BOOST={true,false}
#   enables increased LVDS output current of 6.4mA (default: 3.2mA)
# LVDS_TERM={true,false}
#   enables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only
#
# Global IO constraints can be set with the default_GPIO statement. It can be
# overwritten by individual settings for specific GPIOs, e.g.:
#   default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten
#========================================================================
# GPIO Configuration - Free Bank Selectable Voltage
# Bank Selectable VDD 1.2V/1.8V/2.5V/User PWR_Supply
#========================================================================

# Depending on how you turn the Olimex Board, the orientation of the pins is flipped
# If you turn the board so that you can read the Olimex logo and the VGA Port is to the left then the upper row is GND, NA_B..
# And the lower row is VDD_NA, NA_A... from left to right
#
# If you turn the board so that the VGA Port is pointing up, then the VDD_NA, NA_A pins are to the left, like on the picture of the extension below
# This is the case for the Bank_NA1, Bank_NB1 and Bank_EB1

#========================================================================
#  Bank NA1
#========================================================================

#========================================================================
# BANK_EB1
#========================================================================

#========================================================================
# BANK_MISC1
#========================================================================
# BANK_MISC1 is the big one to the right of the board and the configuration + text-picture below is taking into account that you have
# the Olimex board placed so that the BANK_MISC1 is on the right side(VGA Port is on the left side).
#========================================================================
# Left Row
# TOP LEFT PIN IS 2.5V
#Net "FPGA_RESET_IN" Loc = "RST_N";
#Net "rst_n" Loc = "IO_SB_B8";

#Net "FPGA_LED" Loc = "IO_SB_B6"; # FPGA LED
Net "led0" Loc = "IO_SB_B6"; # FPGA LED
Net "rst_n" Loc = "IO_SB_B7";
#Net "CLK0"     Loc = "IO_SB_A8"; # CLK0
Net "clk"     Loc = "IO_SB_A8" | SCHMIDT_TRIGGER=true ; # CLK0
#========================================================================
# UART Interface
#========================================================================
# There is a mistake on the schematic, these need to be flipped as below
#========================================================================
#Net "DBG_UART_RX" Loc = "IO_SA_A6"; # GPIO12
#Net "DBG_UART_TX" Loc = "IO_SA_B6"; # GPIO13
Net "uart_txd_in" Loc = "IO_SA_A6"; # GPIO12
Net "uart_rxd_out" Loc = "IO_SA_B6"; # GPIO13
#========================================================================
# VGA Configuration
#========================================================================

Net "VGA_HS_O" Loc = "IO_WB_A1";
Net "VGA_VS_O" Loc = "IO_WB_B1";
Net "VGA_R[3]" Loc = "IO_WB_A2";
Net "VGA_R[2]" Loc = "IO_WB_B2";
Net "VGA_R[1]" Loc = "IO_WB_A3";
Net "VGA_R[0]" Loc = "IO_WB_B3";
Net "VGA_G[3]" Loc = "IO_WB_A4";
Net "VGA_G[2]" Loc = "IO_WB_B4";
Net "VGA_G[1]" Loc = "IO_WB_A5";
Net "VGA_G[0]" Loc = "IO_WB_B5";
Net "VGA_B[3]" Loc = "IO_WB_A6";
Net "VGA_B[2]" Loc = "IO_WB_B6";
Net "VGA_B[1]" Loc = "IO_WB_A7";
Net "VGA_B[0]" Loc = "IO_WB_B7";

#========================================================================
## PSRAM Configuration
#========================================================================

#Net "PSRAM_CS"    Loc = "IO_WC_A4";
#Net "PSRAM_SCLK"  Loc = "IO_WC_B4";
#Net "PSRAM_DATA[0]" Loc = "IO_WC_A5";
#Net "PSRAM_DATA[1]" Loc = "IO_WC_B5";
#Net "PSRAM_DATA[2]" Loc = "IO_WC_A6";
#Net "PSRAM_DATA[3]" Loc = "IO_WC_B6";
#Net "PSRAM_DATA[4]" Loc = "IO_WC_A7";
#Net "PSRAM_DATA[5]" Loc = "IO_WC_B7";
#Net "PSRAM_DATA[6]" Loc = "IO_WC_A8";
#Net "PSRAM_DATA[7]" Loc = "IO_WC_B8";

#========================================================================
# PMOD
#========================================================================
                                                #      ___________
#Net "PMOD_1"   Loc = "IO_EA_A4";                #      | 1     7 |   
#Net "PMOD_7"   Loc = "IO_EA_B4";                #      | 2     8 |
#Net "PMOD_2"   Loc = "IO_EA_A5";                #      | 3     9 |
#Net "PMOD_8"   Loc = "IO_EA_B5";                #      | 4    10 |
#Net "PMOD_3"   Loc = "IO_EA_A6";                # GND -| 5    11 | --- GND
#Net "PMOD_9"   Loc = "IO_EA_B6";                # 3-3V-| 6    12 | --- 3.3V
#Net "PMOD_4"   Loc = "IO_EA_B7";                #      ___________
#Net "PMOD_10"  Loc = "IO_EA_A7";