Tridora-CPU/tridoracpu
2026-01-01 02:07:36 +01:00
..
tridoracpu.srcs tdraudio: fix wiring for channel 2, irqctrl: increase delay 2026-01-01 02:07:36 +01:00
sdspi_testbench_behav.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
testbench_behav.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
tridoracpu.xpr tridoracpu: cleaned up top a bit, removed some warnings 2025-12-15 00:53:36 +01:00