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tdraudio: fix wiring for channel 2, irqctrl: increase delay

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slederer 2026-01-01 02:07:36 +01:00
parent d2f3b09e72
commit a9412d1339
2 changed files with 2 additions and 2 deletions
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2
tridoracpu/tridoracpu.srcs/irqctrl.v
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@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module irqctrl #(IRQ_LINES = 3, IRQ_DELAY_WIDTH = 4) (
module irqctrl #(IRQ_LINES = 3, IRQ_DELAY_WIDTH = 8) (
input wire clk,
input wire [IRQ_LINES-1:0] irq_in,
input wire cs,

2
tridoracpu/tridoracpu.srcs/tdraudio.v
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@ -233,7 +233,7 @@ module tdraudio #(DATA_WIDTH=32) (
chan2_rd_data, amp_wr_data,
chan2_rd_en, chan2_wr_en,
chan2_amp,
chan2_irq, chan2_running);
chan2_running, chan2_irq);
wavegen chan3(clk, reset, reg_sel,
chan3_rd_data, amp_wr_data,