Merge pull request 'implement data cache (write-back or write-through)' (#2) from dcache into main

Reviewed-on: #2

examples/benchmarks.results.text

@@ -145,4 +145,27 @@ Running benchmarks.prog
                           exp() 10K 00:00:25
                           cos() 10K 00:00:05
 
+--------------------------------------
+Arty-A7-35T
+76.92MHz, 32KB SRAM, 256MB DRAM,
+  16B instruction cache, 16B wb data cache
+running in DRAM (except corelib, stdlib, runtime)
 
+Running benchmarks.prog
+                     empty loop 10M 00:00:04
+                 write variable 10M 00:00:11
+                  read variable 10M 00:00:18
+               integer addition 10M 00:00:18
+                   real addition 1M 00:00:27
+          integer multiplication 1M 00:00:49
+             real multiplication 1M 00:00:58
+                integer division 1M 00:01:06
+                   real division 1M 00:01:04
+                 string indexing 1M 00:00:36
+                string iteration 1M 00:00:19
+                  new/dispose 1k 1M 00:00:18
+                new/dispose 128k 1M 00:00:18
+                  array copy 1k 10K 00:00:03
+                 array copy 128k 1K 00:00:39
+                          exp() 10K 00:00:25
+                          cos() 10K 00:00:05

lib/sdcardlib.s

@@ -264,8 +264,8 @@ CARD_OK:
 ; set fast transfer rate
 CARDFASTCLK:
 	LOADC SPIREG
-	; set clock divider to ~2,6MHz
+	; set clock divider to ~2.75MHz
-	LOADCP SPI_CLK_DIV_WR,10 ; using the LOADCP with offset syntax here
+	LOADCP SPI_CLK_DIV_WR,7 ; using the LOADCP with offset syntax here
 	STOREI
 	DROP
 	RET

tridoracpu/tridoracpu.xpr

@@ -351,9 +351,7 @@
   <Runs Version="1" Minor="22">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred  with a larger threshold" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Flow_PerfOptimized_high" Flow="Vivado Synthesis 2024">
+        <StratHandle Name="Flow_PerfOptimized_high" Flow="Vivado Synthesis 2024"/>
-          <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred  with a larger threshold</Desc>
-        </StratHandle>
         <Step Id="synth_design">
           <Option Id="Directive">7</Option>
           <Option Id="FsmExtraction">1</Option>
@@ -380,9 +378,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>