4 commits

Author	SHA1	Message	Date
slederer	d2f3b09e72	tridoracpu: cleaned up top a bit, removed some warnings	2025-12-15 00:53:36 +01:00
slederer	d5888861d3	tdraudio: first step of implementing a sound generator	2025-09-23 23:39:04 +02:00
slederer	c2d7c6627a	tridoracpu: reduce clock speed, fix vblank flag in vgafb	2025-03-13 22:37:56 +01:00
slederer	a441e7e042	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00

Renamed from rtl/arty-a7/Arty-A7-35-Master.xdc (Browse further)