5 commits

Author	SHA1	Message	Date
slederer	4d4cc0c535	dram_bridge: cleanup ... - mem_wait must be enabled on each write - dcache_hit is never true on a write, so the ~dcache_hit clause was always true	2025-09-30 00:49:17 +02:00
slederer	278f90a464	tridoracpu: implement data cache	2025-09-15 23:02:22 +02:00
slederer	8abd9fc126	tridoracpu: cache bug fixes	2025-03-29 01:29:16 +01:00
slederer	b6bd487b7e	tridoracpu: first attempt at instruction cache	2025-03-16 00:10:53 +01:00
slederer	a441e7e042	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00

Renamed from rtl/src/dram_bridge.v (Browse further)