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lib: prepare rommon and corelib for different clock speeds

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slederer 2025-03-13 23:15:45 +01:00
parent c2d7c6627a
commit 3f40c50170
2 changed files with 28 additions and 10 deletions
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16
lib/corelib.s
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@ -588,13 +588,19 @@ DIVU_END:
; wait approx. 1 millisecond ; wait approx. 1 millisecond
; ;
; 83.333 MHz Clock, three instructions a 4 cycles ; the ROM at address 4
; 83333 / 12 = 6944.4166 ; contains the cpu clock freq in KHz
; works only if executed without wait states (i.e. .EQU CLK_KHZ_ADDR 4
; from BRAM/SRAM)
WAIT1MSEC: WAIT1MSEC:
LOADCP 6944 LOADC CLK_KHZ_ADDR
LOADI
; divide by 16
SHR
SHR
SHR
SHR
WAIT1LOOP: WAIT1LOOP:
INC 0 ; NOP to make the loop 16 cycles long
DEC 1 DEC 1
DUP DUP
CBRANCH.NZ WAIT1LOOP CBRANCH.NZ WAIT1LOOP

22
lib/rommon.s
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@ -7,8 +7,16 @@
.EQU UART_REG 2048 .EQU UART_REG 2048
.EQU MON_ADDR 64512 .EQU MON_ADDR 64512
.EQU CLK_KHZ 76923
BRANCH 2 ; the very first instruction is not BRANCH 2 ; the very first instruction is not
; executed correctly ; executed correctly
BRANCH MON_START ; branch over constant
CLK_KHZ_ADDR:
.WORD CLK_KHZ ; to calibrate the delay loop
MON_START:
LOADCP 65020 ; initialise FP and RP registers LOADCP 65020 ; initialise FP and RP registers
STOREREG FP STOREREG FP
LOADCP 65024 LOADCP 65024
@ -782,13 +790,17 @@ COPY_BLK1:
; wait approx. 1 millisecond ; wait approx. 1 millisecond
; ;
; 83.333 MHz Clock, three instructions a 4 cycles
; 83333 / 12 = 6944.4166
; works only if executed without wait states (i.e.
; from BRAM/SRAM)
WAIT1MSEC: WAIT1MSEC:
LOADCP 6944 ; get clock freq in khz
LOADC CLK_KHZ_ADDR
LOADI
; divide by 16
SHR
SHR
SHR
SHR
WAIT1LOOP: WAIT1LOOP:
INC 0 ; NOP to make loop 16 cycles long
DEC 1 DEC 1
DUP DUP
CBRANCH.NZ WAIT1LOOP CBRANCH.NZ WAIT1LOOP