From 3f40c50170fec9cbb2e3b7d0a4720f869db9200f Mon Sep 17 00:00:00 2001
From: slederer <dev@insignificance.de>
Date: Thu, 13 Mar 2025 23:15:45 +0100
Subject: [PATCH] lib: prepare rommon and corelib for different clock speeds

---
 lib/corelib.s | 16 +++++++++++-----
 lib/rommon.s  | 22 +++++++++++++++++-----
 2 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/lib/corelib.s b/lib/corelib.s
index 57f35a8..6970971 100644
--- a/lib/corelib.s
+++ b/lib/corelib.s
@@ -588,13 +588,19 @@ DIVU_END:
 
 ; wait approx. 1 millisecond
 ;
-; 83.333 MHz Clock, three instructions a 4 cycles
-; 83333 / 12 = 6944.4166
-; works only if executed without wait states (i.e.
-; from BRAM/SRAM)
+; the ROM at address 4
+; contains the cpu clock freq in KHz
+	.EQU CLK_KHZ_ADDR 4
 WAIT1MSEC:
-	LOADCP 6944
+	LOADC CLK_KHZ_ADDR
+	LOADI
+	; divide by 16
+	SHR
+	SHR
+	SHR
+	SHR
 WAIT1LOOP:
+	INC 0 ; NOP to make the loop 16 cycles long
 	DEC 1
 	DUP
 	CBRANCH.NZ WAIT1LOOP
diff --git a/lib/rommon.s b/lib/rommon.s
index a967e4b..4828008 100644
--- a/lib/rommon.s
+++ b/lib/rommon.s
@@ -7,8 +7,16 @@
 	.EQU UART_REG 2048
 	.EQU MON_ADDR 64512
 
+	.EQU CLK_KHZ 76923
+
 	BRANCH 2	; the very first instruction is not
 			; executed correctly
+	BRANCH MON_START ; branch over constant
+
+CLK_KHZ_ADDR:
+	.WORD CLK_KHZ  ; to calibrate the delay loop
+
+MON_START:
 	LOADCP 65020 ; initialise FP and RP registers
 	STOREREG FP
 	LOADCP 65024
@@ -782,13 +790,17 @@ COPY_BLK1:
 
 ; wait approx. 1 millisecond
 ;
-; 83.333 MHz Clock, three instructions a 4 cycles
-; 83333 / 12 = 6944.4166
-; works only if executed without wait states (i.e.
-; from BRAM/SRAM)
 WAIT1MSEC:
-	LOADCP 6944
+	; get clock freq in khz
+	LOADC CLK_KHZ_ADDR
+	LOADI
+	; divide by 16
+	SHR
+	SHR
+	SHR
+	SHR
 WAIT1LOOP:
+	INC 0	; NOP to make loop 16 cycles long
 	DEC 1
 	DUP
 	CBRANCH.NZ WAIT1LOOP