lib: prepare rommon and corelib for different clock speeds

lib/corelib.s

@@ -588,13 +588,19 @@ DIVU_END:
 
 ; wait approx. 1 millisecond
 ;
-; 83.333 MHz Clock, three instructions a 4 cycles
-; 83333 / 12 = 6944.4166
-; works only if executed without wait states (i.e.
-; from BRAM/SRAM)
+; the ROM at address 4
+; contains the cpu clock freq in KHz
+	.EQU CLK_KHZ_ADDR 4
 WAIT1MSEC:
-	LOADCP 6944
+	LOADC CLK_KHZ_ADDR
+	LOADI
+	; divide by 16
+	SHR
+	SHR
+	SHR
+	SHR
 WAIT1LOOP:
+	INC 0 ; NOP to make the loop 16 cycles long
 	DEC 1
 	DUP
 	CBRANCH.NZ WAIT1LOOP