36 lines
1.7 KiB
Markdown
36 lines
1.7 KiB
Markdown
# Memory Layout
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The Tridora system uses the following memory layout:
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|Address (hex) |Address (decimal)|Description|
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|-------|-----------|------------------------|
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|$00000000| 0 | ROM |
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|$00000800| 2048 | I/O area|
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|$00001000| 4096 | RAM (SRAM)|
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|$00010000| 65536 | RAM (DRAM)|
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## Accessing Words and Bytes
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Memory is word-oriented, so there is no access to individual bytes. Memory transfers always use 32 bits.
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Word addresses in RAM and ROM use an increment of 4, so the first memory word is at address 0, the second is at address 4 etc.
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This way, you can express a pointer to a specific byte within a word.
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The lower two bits of the address are ignored when accessing RAM or ROM. So if you use 1 as a memory address, you still get the memory word at address 0.
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The lower two bits of the address can be viewed as a byte address (0-3) within the word.
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The _BSEL_ and _BPLC_ instructions are designed to assist with accessing bytes within a word.
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The byte ordering is big-endian.
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## Accessing the I/O Area
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The I/O area organizes memory slightly different. Here, pointing out individual bytes is not very useful, so the I/O controllers use register addresses with increments of one. In practice, there is only the VGA framebuffer controller which uses multiple registers.
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The individual I/O controllers each have a memory area of 128 bytes, so there is a maximum number of 16 I/O controllers.
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Currently, only I/O slots 0-3 are being used.
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|I/O slot| Address | Controller |
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|--------|---------|------------|
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| 0 | $800 | UART |
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| 1 | $880 | SPI-SD |
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| 2 | $900 | VGA |
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| 3 | $980 | IRQC |
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