48 lines
1.7 KiB
Markdown
48 lines
1.7 KiB
Markdown
# Interrupt Controller
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The interrupt controller uses a single register at address: $980
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## Reading the status register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|t |t |t |t |t |t |t |t |t |t|t |t |t |t |t |t |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|t |t |t |t |t |t |t |t |- |- |- |- |- |- |p1 |p0 |
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|Bitfields|Description|
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|---------|-----------|
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| _t_ | unsigned 24 bit counter of timer ticks since reset
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| _p1_ | IRQ 1 (timer tick) interrupt pending if 1
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| _p0_ | IRQ 0 (UART) interrupt pending if 1
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## Writing the status register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |i |- |- |- |- |- |- |- |
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|Bitfields|Description|
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|---------|-----------|
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| _i_ | 1 = interrupts enabled, 0 = interrupts disabled
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## Notes
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Interrupt processing is disabled on reset and needs to be enabled by writing a value with
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bit 7 set to the status register (i.e. 127).
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An interrupt is only signaled once to the CPU whenever one of the IRQ signals becomes active.
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Reading the status register will reflect all pending interrupts since enabling interrupt processing.
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Interrupt processing needs to be re-enabled after an interrupt occurs by setting bit 7 in the status register again. This will also clear all pending interrupts.
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