74 lines
2 KiB
Verilog
74 lines
2 KiB
Verilog
`timescale 1ns / 1ps
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module tdraudio #(DATA_WIDTH=32) (
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input wire clk,
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input wire reset,
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input wire [3:0] reg_sel,
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output wire [DATA_WIDTH-1:0] rd_data,
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input wire [DATA_WIDTH-1:0] wr_data,
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input wire rd_en,
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input wire wr_en,
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output wire pdm_out,
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output wire gain_en,
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output wire shutdown_n
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);
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localparam CLOCK_DIV_WIDTH = 22;
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localparam TDRAU_REG_CTL = 0; /* control register */
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localparam TDRAU_REG_CLK = 1; /* clock divider register */
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reg audio_out;
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reg channel_enable;
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reg [CLOCK_DIV_WIDTH-1:0] clock_div;
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reg [CLOCK_DIV_WIDTH-1:0] div_count;
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assign pdm_out = audio_out;
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assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
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assign gain_en = 0;
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assign shutdown_n = channel_enable;
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/* channel enable flag */
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always @(posedge clk)
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begin
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if(reset)
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channel_enable <= 0;
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else if (wr_en && (reg_sel == TDRAU_REG_CTL))
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channel_enable <= wr_data[0];
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end
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/* clock divider register */
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always @(posedge clk)
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begin
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if(reset)
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clock_div <= 0;
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else if (wr_en && (reg_sel == TDRAU_REG_CLK))
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clock_div <= wr_data;
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end
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/* divider counter */
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always @(posedge clk)
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begin
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if(channel_enable)
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begin
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if(div_count == 0) // reset counter if it reaches zero
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div_count <= clock_div;
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else
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div_count <= div_count - 1; // else just decrement it
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end
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else
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if (wr_en && (reg_sel == TDRAU_REG_CLK))
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div_count <= 0; // set counter to zero whenever the clock divider is set
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end
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/* 1-bit audio output */
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always @(posedge clk)
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begin
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if (reset)
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audio_out <= 0;
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else
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if (channel_enable && (div_count == 0))
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audio_out <= ~audio_out;
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end
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endmodule
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