59 lines
1.2 KiB
Makefile
59 lines
1.2 KiB
Makefile
SRCDIR := tridoracpu.srcs
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TOOLCHAIN := $(CC_TOOL)
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YOSYS = $(TOOLCHAIN)/bin/yosys/yosys$(EXE)
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PNR = $(TOOLCHAIN)/bin/p_r/p_r$(EXE)
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OFL = openFPGAloader
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IVLFLAGS = -g2012 -gspecify -Ttyp
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OFLFLAGS = --cable dirtyJtag
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TOP = top
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CONSTR = $(SRCDIR)/GateMateA1-EVB.ccf
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PNRFLAGS += -ccf $(CONSTR) -cCP
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SYNTHFILE = build/$(TOP)_synth.v
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BITSTREAM = build/$(TOP)_00.cfg.bit
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srcs = \
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$(SRCDIR)/bram_tdp.v \
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$(SRCDIR)/fifo.v \
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$(SRCDIR)/irqctrl.v \
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$(SRCDIR)/palette.v \
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$(SRCDIR)/sdspi.v \
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$(SRCDIR)/stackcpu.v \
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$(SRCDIR)/stack.v \
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$(SRCDIR)/uart.v
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# also modify top.v to enable vgafb
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#srcs += $(SRCDIR)/vgafb.v
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# for CCGMA1-EVB
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srcs += $(SRCDIR)/cpuclk_ccgm.v $(SRCDIR)/top_ccgm.v $(SRCDIR)/mem_ccgm.v
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# for Arty-A7
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# src += $(SRCDIR)/cpuclk.v $(SRCDIR)/top.v $(SRCDIR)/mem.v
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all: build synth impl
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clean:
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rm -rf build
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.PHONY: all clean
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build:
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mkdir $@
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synth: $(SYNTHFILE)
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impl: $(BITSTREAM)
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$(SYNTHFILE): $(srcs)
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$(YOSYS) -ql build/synth.log -p 'read -sv $(srcs); synth_gatemate -top $(TOP) -nomx8 -vlog $(SYNTHFILE)'
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$(BITSTREAM): $(SYNTHFILE)
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$(PNR) -v -i $(SYNTHFILE) -o build/$(TOP) $(PNRFLAGS) | tee $@.log
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prog: $(BITSTREAM)
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$(OFL) $(OFLFLAGS) --bitstream $(BITSTREAM)
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