SRCDIR := tridoracpu.srcs
TOOLCHAIN := $(CC_TOOL)

YOSYS = $(TOOLCHAIN)/bin/yosys/yosys$(EXE)
PNR   = $(TOOLCHAIN)/bin/p_r/p_r$(EXE)
OFL   = openFPGAloader

IVLFLAGS = -g2012 -gspecify -Ttyp
OFLFLAGS = --cable dirtyJtag

TOP      = top
CONSTR   = $(SRCDIR)/GateMateA1-EVB.ccf
PNRFLAGS += -ccf $(CONSTR) -cCP

SYNTHFILE = build/$(TOP)_synth.v

BITSTREAM = build/$(TOP)_00.cfg.bit

srcs = \
    $(SRCDIR)/bram_tdp.v \
    $(SRCDIR)/fifo.v \
    $(SRCDIR)/irqctrl.v \
    $(SRCDIR)/palette.v \
    $(SRCDIR)/sdspi.v \
    $(SRCDIR)/stackcpu.v \
    $(SRCDIR)/stack.v \
    $(SRCDIR)/uart.v

# also modify top.v to enable vgafb
#srcs += $(SRCDIR)/vgafb.v

# for CCGMA1-EVB
srcs += $(SRCDIR)/cpuclk_ccgm.v $(SRCDIR)/top_ccgm.v $(SRCDIR)/mem_ccgm.v

# for Arty-A7
# src += $(SRCDIR)/cpuclk.v $(SRCDIR)/top.v $(SRCDIR)/mem.v

all: build synth impl
clean:
	rm -rf build

.PHONY: all clean

build:
	mkdir $@

synth: $(SYNTHFILE)
impl: $(BITSTREAM)


$(SYNTHFILE): $(srcs)
	$(YOSYS) -ql build/synth.log -p 'read -sv $(srcs); synth_gatemate -top $(TOP) -nomx8 -vlog $(SYNTHFILE)'

$(BITSTREAM): $(SYNTHFILE)
	$(PNR) -v -i $(SYNTHFILE) -o build/$(TOP) $(PNRFLAGS) | tee $@.log

prog: $(BITSTREAM)
	$(OFL) $(OFLFLAGS) --bitstream $(BITSTREAM)