85 lines
4.1 KiB
Verilog
85 lines
4.1 KiB
Verilog
`timescale 1ns / 1ps
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module cpu_clkgen(
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input wire rst,
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input wire clk100,
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output wire cpuclk,
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output wire dram_refclk,
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output wire pixclk,
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output wire locked
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);
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wire cpuclk_pre, clk_fb, refclk_pre, pixclk_pre;
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MMCME2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
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.CLKFBOUT_MULT_F(10.0), // Multiply value for all CLKOUT (2.000-64.000).
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
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.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
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// CPU Clock: 12.0 = 83.33MHz CPU Clock, 333.33MHz Memory Clock
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// 13.0 = 76.92MHz CPU Clock, 307.69MHz Memory Clock
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.CLKOUT0_DIVIDE_F(13.0), // Divide amount for CLKOUT0 (1.000-128.000).
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.CLKOUT1_DIVIDE(5),
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.CLKOUT2_DIVIDE(40), // 40 = 25MHz pixel clock (should be 25.175MHz per spec) for 640x480
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//.CLKOUT2_DIVIDE(25), // 25 = 40MHz pixel clock for 800x600
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//.CLKOUT2_DIVIDE(15), // 15 = 66.66MHz pixel clock (should be 65.0Mhz per spec) for 1024x768
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.CLKOUT3_DIVIDE(1),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT6_DIVIDE(1),
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// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT6_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT6_PHASE(0.0),
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.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
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.DIVCLK_DIVIDE(1), // Master division value (1-106)
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.REF_JITTER1(0.010), // Reference input jitter in UI (0.000-0.999).
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.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE)
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)
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MMCME2_BASE_inst (
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/* verilator lint_off PINCONNECTEMPTY */
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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.CLKOUT0(cpuclk_pre), // 1-bit output: CLKOUT0
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.CLKOUT0B(), // 1-bit output: Inverted CLKOUT0
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.CLKOUT1(refclk_pre), // 1-bit output: CLKOUT1
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.CLKOUT1B(), // 1-bit output: Inverted CLKOUT1
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.CLKOUT2(pixclk_pre), // 1-bit output: CLKOUT2
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.CLKOUT2B(), // 1-bit output: Inverted CLKOUT2
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.CLKOUT3(), // 1-bit output: CLKOUT3
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.CLKOUT3B(), // 1-bit output: Inverted CLKOUT3
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.CLKOUT4(), // 1-bit output: CLKOUT4
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.CLKOUT5(), // 1-bit output: CLKOUT5
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.CLKOUT6(), // 1-bit output: CLKOUT6
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// Feedback Clocks: 1-bit (each) output: Clock feedback ports
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.CLKFBOUT(clk_fb), // 1-bit output: Feedback clock
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.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
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// Status Ports: 1-bit (each) output: MMCM status ports
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.LOCKED(locked), // 1-bit output: LOCK
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// Clock Inputs: 1-bit (each) input: Clock input
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.CLKIN1(clk100), // 1-bit input: Clock
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// Control Ports: 1-bit (each) input: MMCM control ports
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.PWRDWN(), // 1-bit input: Power-down
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/* verilator lint_on PINCONNECTEMPTY */
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.RST(rst), // 1-bit input: Reset
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// Feedback Clocks: 1-bit (each) input: Clock feedback ports
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.CLKFBIN(clk_fb) // 1-bit input: Feedback clock
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);
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BUFG bufg_cpuclk(.I(cpuclk_pre), .O(cpuclk));
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BUFG bufg_refclk(.I(refclk_pre), .O(dram_refclk));
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BUFG bufg_pixclk(.I(pixclk_pre), .O(pixclk));
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endmodule
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