294 lines
11 KiB
Verilog
294 lines
11 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// Project F: Display Timings
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// (C)2019 Will Green, Open Source Hardware released under the MIT License
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// Learn more at https://projectf.io
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//128K video memory is not enough for 640x480x4
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`define RES_640_400
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//`define RES_1024_768
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module display_timings #(
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H_RES=640, // horizontal resolution (pixels)
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V_RES=480, // vertical resolution (lines)
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H_FP=16, // horizontal front porch
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H_SYNC=96, // horizontal sync
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H_BP=48, // horizontal back porch
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V_FP=10, // vertical front porch
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V_SYNC=2, // vertical sync
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V_BP=33, // vertical back porch
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H_POL=0, // horizontal sync polarity (0:neg, 1:pos)
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V_POL=0 // vertical sync polarity (0:neg, 1:pos)
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)
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(
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input wire i_pix_clk, // pixel clock
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input wire i_rst, // reset: restarts frame (active high)
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output wire o_hs, // horizontal sync
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output wire o_vs, // vertical sync
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output wire o_de, // display enable: high during active video
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output wire o_frame, // high for one tick at the start of each frame
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output wire o_scanline, // high for one tick at the start of each scanline
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output reg o_vblank, // high during vertical blank phase
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output reg signed [15:0] o_sx, // horizontal beam position (including blanking)
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output reg signed [15:0] o_sy // vertical beam position (including blanking)
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);
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// Horizontal: sync, active, and pixels
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localparam signed H_STA = 0 - H_FP - H_SYNC - H_BP; // horizontal start
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localparam signed HS_STA = H_STA + H_FP; // sync start
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localparam signed HS_END = HS_STA + H_SYNC; // sync end
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localparam signed HA_STA = 0; // active start
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localparam signed HA_END = H_RES - 1; // active end
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// Vertical: sync, active, and pixels
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localparam signed V_STA = 0 - V_FP - V_SYNC - V_BP; // vertical start
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localparam signed VS_STA = V_STA + V_FP; // sync start
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localparam signed VS_END = VS_STA + V_SYNC; // sync end
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localparam signed VA_STA = 0; // active start
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localparam signed VA_END = V_RES - 1; // active end
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// generate sync signals with correct polarity
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assign o_hs = H_POL ? (o_sx > HS_STA && o_sx <= HS_END)
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: ~(o_sx > HS_STA && o_sx <= HS_END);
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assign o_vs = V_POL ? (o_sy > VS_STA && o_sy <= VS_END)
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: ~(o_sy > VS_STA && o_sy <= VS_END);
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// display enable: high during active period
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assign o_de = (o_sx >= 0 && o_sy >= 0);
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// o_frame: high for one tick at the start of each frame
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assign o_frame = (o_sy == V_STA && o_sx == H_STA);
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// o_scanline: high for one tick at the start of each visible scanline
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assign o_scanline = (o_sy >= VA_STA) && (o_sy <= VA_END) && (o_sx == H_STA);
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// set vblank at end of frame, clear at start
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always @(posedge i_pix_clk)
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begin
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if(o_sy == VA_END) o_vblank <= 1;
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else if (o_sy == -1) o_vblank <= 0;
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end
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always @ (posedge i_pix_clk)
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begin
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if (i_rst) // reset to start of frame
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begin
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o_sx <= H_STA;
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o_sy <= V_STA;
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end
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else
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begin
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if (o_sx == HA_END) // end of line
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begin
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o_sx <= H_STA;
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if (o_sy == VA_END) // end of frame
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o_sy <= V_STA;
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else
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o_sy <= o_sy + 16'sh1;
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end
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else
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o_sx <= o_sx + 16'sh1;
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end
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end
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endmodule
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// Project F: Display Controller VGA Demo
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// (C)2020 Will Green, Open source hardware released under the MIT License
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// Learn more at https://projectf.io
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// This demo requires the following Verilog modules:
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// * display_clocks
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// * display_timings
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// * test_card_simple or another test card
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module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
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input wire cpu_clk, // cpu clock
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input wire CLK, // pixel clock
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input wire RST_BTN, // reset button
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input wire[3:0] reg_sel, // register select/address
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output wire [VMEM_DATA_WIDTH-1:0] rd_data,
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input wire [VMEM_DATA_WIDTH-1:0] wr_data,
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input wire rd_en,
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input wire wr_en,
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output wire VGA_HS, // horizontal sync output
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output wire VGA_VS, // vertical sync output
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output wire [3:0] VGA_R, // 4-bit VGA red output
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output wire [3:0] VGA_G, // 4-bit VGA green output
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output wire [3:0] VGA_B // 4-bit VGA blue output
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);
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localparam BITS_PER_PIXEL = 4; localparam MAX_SHIFT_COUNT = 7;
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localparam REG_RD_ADDR = 0; localparam REG_WR_ADDR = 1; localparam REG_VMEM = 2;
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localparam REG_PAL_SLOT = 3; localparam REG_PAL_DATA = 4;
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localparam REG_CTL = 5;
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localparam COLOR_WIDTH = 12;
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localparam PALETTE_WIDTH = 4;
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// Display Clocks
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wire pix_clk = CLK; // pixel clock
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wire clk_lock = 1; // clock locked?
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wire vmem_rd_en;
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wire vmem_wr_en;
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wire [VMEM_DATA_WIDTH-1:0] vmem_rd_data;
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reg [VMEM_ADDR_WIDTH-1:0] cpu_rd_addr;
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reg [VMEM_ADDR_WIDTH-1:0] cpu_wr_addr;
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reg [VMEM_ADDR_WIDTH-1:0] pix_addr;
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wire [VMEM_DATA_WIDTH-1:0] pix_data;
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wire pix_rd;
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wire [VMEM_DATA_WIDTH-1:0] status;
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assign vmem_rd_en = rd_en;
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assign vmem_wr_en = (reg_sel == REG_VMEM) && wr_en;
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assign rd_data = (reg_sel == REG_VMEM) ? vmem_rd_data :
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(reg_sel == REG_RD_ADDR) ? cpu_rd_addr :
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(reg_sel == REG_WR_ADDR) ? cpu_wr_addr :
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(reg_sel == REG_CTL) ? status :
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32'hFFFFFFFF;
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wire [VMEM_ADDR_WIDTH-1:0] cpu_addr = vmem_wr_en ? cpu_wr_addr : cpu_rd_addr;
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bram_tdp #(.DATA(VMEM_DATA_WIDTH),.ADDR(VMEM_ADDR_WIDTH)) vram0 (
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.a_rd(vmem_rd_en), .a_clk(cpu_clk),
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.a_wr(vmem_wr_en), .a_addr(cpu_addr), .a_din(wr_data),
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.a_dout(vmem_rd_data),
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.b_clk(pix_clk), .b_addr(pix_addr), .b_dout(pix_data),
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.b_rd(pix_rd)
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);
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wire palette_wr_en = (reg_sel == REG_PAL_DATA) && wr_en;
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reg [PALETTE_WIDTH-1:0] palette_wr_slot;
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wire [COLOR_WIDTH-1:0] color_data;
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palette palette0(.wr_clk(cpu_clk), .rd_clk(pix_clk), .wr_en(palette_wr_en),
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.wr_slot(palette_wr_slot), .wr_data(wr_data[COLOR_WIDTH-1:0]),
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.rd_slot(pixel[3:0]), .rd_data(color_data));
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// Display Timings
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wire signed [15:0] sx; // horizontal screen position (signed)
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wire signed [15:0] sy; // vertical screen position (signed)
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wire h_sync; // horizontal sync
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wire v_sync; // vertical sync
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wire de; // display enable
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wire frame; // frame start
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wire scanline; // scanline start
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wire vblank; // vertical blank
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reg vblank_buf; // vertical blank in cpu clock domain
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reg vblank_xfer; // vertical blank clock domain crossing
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display_timings #( // 640x480 800x600 1280x720 1920x1080
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`ifdef RES_1024_768
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.H_RES(1024), // 640 800 1280 1920
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.V_RES(768), // 480 600 720 1080
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.H_FP(24), // 16 40 110 88
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.H_SYNC(136), // 96 128 40 44
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.H_BP(160), // 48 88 220 148
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.V_FP(3), // 10 1 5 4
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.V_SYNC(6), // 2 4 5 5
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.V_BP(29), // 33 23 20 36
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.H_POL(0), // 0 1 1 1
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.V_POL(0) // 0 1 1 1
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`endif
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`ifdef RES_640_400
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.H_RES(640),
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.V_RES(400),
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.H_FP(16),
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.H_SYNC(96),
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.H_BP(48),
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.V_FP(12),
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.V_SYNC(2),
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.V_BP(35),
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.H_POL(0),
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.V_POL(1)
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`endif
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)
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display_timings_inst (
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.i_pix_clk(CLK),
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.i_rst(!RST_BTN),
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.o_hs(h_sync),
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.o_vs(v_sync),
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.o_de(de),
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.o_frame(frame),
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.o_scanline(scanline),
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.o_vblank(vblank),
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.o_sx(sx),
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.o_sy(sy)
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);
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wire [7:0] red;
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wire [7:0] green;
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wire [7:0] blue;
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reg [VMEM_DATA_WIDTH-1:0] shifter;
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reg [4:0] shift_count;
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// delayed frame signal for pix_rd
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reg frame_d;
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assign pix_rd = frame_d || scanline || (shift_count == 2);
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assign status = { 4'b0001, {(VMEM_DATA_WIDTH-5){1'b0}}, vblank_buf};
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wire [BITS_PER_PIXEL-1:0] pixel = shifter[VMEM_DATA_WIDTH-1:VMEM_DATA_WIDTH-BITS_PER_PIXEL];
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always @(posedge pix_clk) frame_d <= frame;
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always @(posedge cpu_clk) { vblank_buf, vblank_xfer } <= { vblank_xfer, vblank };
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always @(posedge cpu_clk)
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begin
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if(wr_en)
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begin
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case(reg_sel)
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REG_RD_ADDR: cpu_rd_addr <= wr_data;
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REG_WR_ADDR: cpu_wr_addr <= wr_data;
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REG_VMEM: cpu_wr_addr <= cpu_wr_addr + 1; // auto-increment write addr on write
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REG_PAL_SLOT: palette_wr_slot <= wr_data[3:0];
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endcase
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end
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else
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if(rd_en && reg_sel == REG_VMEM) cpu_rd_addr <= cpu_rd_addr + 1; // auto-increment read addr on read
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end
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always @(posedge pix_clk)
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begin
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if(scanline || shift_count == MAX_SHIFT_COUNT) // before start of a line
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begin // or at the end of a word, reset shifter with pixel data
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shift_count <= 0;
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shifter <= pix_data;
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end
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else if(de)
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begin
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shift_count <= shift_count + 1;
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shifter <= shifter << BITS_PER_PIXEL;
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end
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if(frame) // at start of frame, reset pixel pointer
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pix_addr <= 0;
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else if(shift_count == 1) // after the first pixel, increment address
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pix_addr <= pix_addr + 1;
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end
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// Hard-Coded RGBI palette
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// // Pixel = { red, green, blue, intensity }
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// assign red = pixel[3] ? pixel[0] ? 255 : 127: 0;
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// assign green = pixel[2] ? pixel[0] ? 255 : 127: 0;
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// assign blue = pixel[1] ? pixel[0] ? 255 : 127: 0;
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// // VGA Output
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// // VGA Pmod is 12-bit so we take the upper nibble of each colour
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// assign VGA_HS = h_sync;
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// assign VGA_VS = v_sync;
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// assign VGA_R = de ? red[7:4] : 4'b0;
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// assign VGA_G = de ? green[7:4] : 4'b0;
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// assign VGA_B = de ? blue[7:4] : 4'b0;
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// 12 bit RGB palette
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assign VGA_HS = h_sync;
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assign VGA_VS = v_sync;
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assign VGA_R = de ? color_data[11:8] : 4'b0;
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assign VGA_G = de ? color_data[7:4] : 4'b0;
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assign VGA_B = de ? color_data[3:0] : 4'b0;
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endmodule
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