..
mig_dram_0
tridoracpu: update MIG configuration for Vivado 2024
2025-05-24 23:25:57 +02:00
Arty-A7-35-Master.xdc
tridoracpu: reduce clock speed, fix vblank flag in vgafb
2025-03-13 22:37:56 +01:00
bram_tdp.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
cpuclk.v
tridoracpu: reduce clock speed, fix vblank flag in vgafb
2025-03-13 22:37:56 +01:00
display_clock.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
dram_bridge.v
tridoracpu: cache bug fixes
2025-03-29 01:29:16 +01:00
fifo.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
fifo_testbench.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
irqctrl.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
mem.v
stdlib: start with valid random seed; other small changes
2025-03-09 01:57:11 +01:00
palette.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
sdspi.v
tridoracpu: cache bug fixes
2025-03-29 01:29:16 +01:00
sdspi_testbench.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
sfifo.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
stack.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
stackcpu.v
tridoracpu: first attempt at instruction cache
2025-03-16 00:10:53 +01:00
testbench.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
top.v
tridoracpu: cache bug fixes
2025-03-29 01:29:16 +01:00
uart.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
uart_tb.v
import Vivado project, rearrange Verilog sources
2024-09-27 22:14:57 +02:00
vgafb.v
vga framebuffer: use 640x480@60Hz video timings
2025-06-22 00:33:02 +02:00