VGA Controller
Registers
| Name |
Address |
Description |
| FB_RA |
$900 |
Read Address |
| FB_WA |
$901 |
Write Address |
| FB_IO |
$902 |
I/O Register |
| FB_PS |
$903 |
Palette Select |
| FB_PD |
$904 |
Palette Data |
| FB_CTL |
$905 |
Control Register |
Pixel Data
Pixel data is organized in 32-bit-words. With four bits per pixel, one word
contains eight pixels.
| bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| Value |
p0 |
p0 |
p0 |
p0 |
p1 |
p1 |
p1 |
p1 |
p2 |
p2 |
p2 |
p2 |
p3 |
p3 |
p3 |
p3 |
| bit |
15 |
14 |
13 |
12 |
11 |
10 |
09 |
08 |
07 |
06 |
05 |
04 |
03 |
02 |
01 |
00 |
| Value |
p4 |
p4 |
p4 |
p4 |
p5 |
p5 |
p5 |
p5 |
p6 |
62 |
p6 |
p6 |
p7 |
p7 |
p7 |
p7 |
| Bitfields |
Description |
| p0 |
4 bits color value (leftmost pixel) |
| p1 |
4 bits color value |
| p2 |
4 bits color value |
| p3 |
4 bits color value |
| p4 |
4 bits color value |
| p5 |
4 bits color value |
| p6 |
4 bits color value |
| p7 |
4 bits color value (rightmost pixel) |
Video memory uses a linear layout, with words using an address increment of one.
The first word (horizontal pixel coordinates 0-3) is at address 0, the second (coordinates 4-7) at address 1 etc.
The first line starts at address 0, the second at address 80 etc.
To access video memory, the corresponding video memory address must be written to a latch register, then pixel data can be read or written by the I/O register. Reading and writing uses separate latch registers (the "Read Adress" and "Write Address" registers, FB_RA and FB_WA). To read the same word and write it back, both addresses need to be set.
Both registers have an auto-increment function. After reading the I/O register, the FB_RA register is ingremented by one. After writing to the I/O register, the FB_WA register is incremented by one.
Palette Data
The VGA controller uses a 16 color palette. The palette can be changed with the FB_PS and FB_PD registers. Writing to the FB_PS register selects a palette slot. Valid values are 0-15. After a palette slot is selected, color data can be read from and written to the FB_PD register. Color data is organized as follows:
| bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| Value |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
| bit |
15 |
14 |
13 |
12 |
11 |
10 |
09 |
08 |
07 |
06 |
05 |
04 |
03 |
02 |
01 |
00 |
| Value |
- |
- |
- |
- |
r |
r |
r |
r |
g |
g |
g |
g |
b |
b |
b |
b |
| Bitfields |
Description |
| r |
4 bits red intensity |
| g |
4 bits green intensity |
| b |
4 bits blue intensity |
The FB_PS and PB_FD registers cannot be read.
Control Register
The control register contains status information. It can only be read.
| bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| Value |
m |
m |
m |
m |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
| bit |
15 |
14 |
13 |
12 |
11 |
10 |
09 |
08 |
07 |
06 |
05 |
04 |
03 |
02 |
01 |
00 |
| Value |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
vb |
| Bitfields |
Description |
| m |
4 bits mode indicator |
| vb |
vertical blank |
The m field indicates the current graphics mode. At the time of writing, it is
always 1 which denotes a 640x400x4 mode.
The vb bit is 1 when the video signal generator is in its vertical blank phase.
