4d4cc0c535
- mem_wait must be enabled on each write - dcache_hit is never true on a write, so the ~dcache_hit clause was always true
230 lines
8.9 KiB
Verilog
230 lines
8.9 KiB
Verilog
`timescale 1ns / 1ps
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module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
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(
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// local bus
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input wire [ADDR_WIDTH-1:0] mem_addr,
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output wire [WIDTH-1:0] mem_read_data,
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input wire [WIDTH-1:0] mem_write_data,
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input wire mem_read_enable,
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input wire mem_write_enable,
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input wire mem_read_ins,
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output wire mem_wait,
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input wire rst_n,
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input wire dram_front_clk,
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input wire dram_refclk,
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// DDR3 SDRAM
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inout wire [15:0] ddr3_dq,
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inout wire [1:0] ddr3_dqs_n,
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inout wire [1:0] ddr3_dqs_p,
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output wire [13:0] ddr3_addr,
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output wire [2:0] ddr3_ba,
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output wire ddr3_ras_n,
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output wire ddr3_cas_n,
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output wire ddr3_we_n,
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output wire ddr3_reset_n,
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output wire [0:0] ddr3_ck_p,
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output wire [0:0] ddr3_ck_n,
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output wire [0:0] ddr3_cke,
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output wire [0:0] ddr3_cs_n,
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output wire [1:0] ddr3_dm,
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output wire [0:0] ddr3_odt
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);
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localparam DRAM_ADDR_WIDTH = 28, DRAM_DATA_WIDTH = 128, DRAM_MASK_WIDTH = 16;
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wire [DRAM_ADDR_WIDTH-1:0] app_addr;
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wire [2:0] app_cmd;
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wire app_en;
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wire app_rdy;
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wire [DRAM_DATA_WIDTH-1:0] app_rd_data;
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wire app_rd_data_end;
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wire app_rd_data_valid;
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wire [DRAM_DATA_WIDTH-1:0] app_wdf_data;
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wire app_wdf_end;
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wire [DRAM_MASK_WIDTH-1:0] app_wdf_mask;
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wire app_wdf_rdy;
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wire app_sr_active;
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wire app_ref_ack;
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wire app_zq_ack;
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wire app_wdf_wren;
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wire [11:0] device_temp;
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wire ui_clk, ui_rst_sync;
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wire init_calib_complete;
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localparam CMD_READ = 3'b1;
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localparam CMD_WRITE = 3'b0;
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mig_dram_0 dram0(
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// Inouts
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.ddr3_dq(ddr3_dq),
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.ddr3_dqs_n(ddr3_dqs_n),
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.ddr3_dqs_p(ddr3_dqs_p),
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// Outputs
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.ddr3_addr(ddr3_addr),
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.ddr3_ba(ddr3_ba),
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.ddr3_ras_n(ddr3_ras_n),
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.ddr3_cas_n(ddr3_cas_n),
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.ddr3_we_n(ddr3_we_n),
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.ddr3_reset_n(ddr3_reset_n),
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.ddr3_ck_p(ddr3_ck_p),
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.ddr3_ck_n(ddr3_ck_n),
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.ddr3_cke(ddr3_cke),
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.ddr3_cs_n(ddr3_cs_n),
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.ddr3_dm(ddr3_dm),
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.ddr3_odt(ddr3_odt),
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// Application interface ports
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.app_addr (app_addr),
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.app_cmd (app_cmd),
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.app_en (app_en),
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.app_wdf_data (app_wdf_data),
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.app_wdf_mask (app_wdf_mask),
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.app_wdf_end (app_wdf_end),
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.app_wdf_wren (app_wdf_wren),
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.app_rd_data (app_rd_data),
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.app_rd_data_end (app_rd_data_end),
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.app_rd_data_valid (app_rd_data_valid),
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.app_rdy (app_rdy),
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.app_wdf_rdy (app_wdf_rdy),
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.app_sr_req (1'b0),
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.app_ref_req (1'b0),
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.app_zq_req (1'b0),
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.app_sr_active (app_sr_active),
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.app_ref_ack (app_ref_ack),
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.app_zq_ack (app_zq_ack),
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.ui_clk (ui_clk),
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.ui_clk_sync_rst (ui_rst_sync),
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// System Clock Ports
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.sys_clk_i (dram_front_clk),
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// Reference Clock Ports
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.clk_ref_i (dram_refclk),
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.device_temp (device_temp),
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.init_calib_complete (init_calib_complete),
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.sys_rst (rst_n)
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);
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(*KEEP*) reg [DRAM_DATA_WIDTH-1:0] ins_cache;
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(*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] icached_addr;
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(*KEEP*) wire icache_hit = mem_read_enable && mem_read_ins && (icached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
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(*KEEP*) reg [DRAM_DATA_WIDTH-1:0] d_cache;
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(*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] dcached_addr;
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(*KEEP*) wire dcache_hit = mem_read_enable && !mem_read_ins && (dcached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
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wire cache_hit = icache_hit | dcache_hit;
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reg [WIDTH-1:0] read_buf;
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reg read_inprogress = 0;
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wire dram_read_enable = mem_read_enable && !cache_hit;
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assign app_rd_data_end = 1'b1;
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// addresses on the memory interface are aligned to 16 bytes
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// and 28 bits wide (=256MB)
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assign app_addr = { mem_addr[DRAM_ADDR_WIDTH:4], 4'b0000 };
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// select a word from the 128 bits transferred by the dram controller
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// according to the lower bits of the address (ignoring bits 1:0)
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wire [1:0] word_sel = mem_addr[3:2];
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wire [WIDTH-1:0] read_word =
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word_sel == 2'b11 ? app_rd_data[31:0] :
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word_sel == 2'b10 ? app_rd_data[63:32] :
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word_sel == 2'b01 ? app_rd_data[95:64] :
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app_rd_data[127:96];
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wire [WIDTH-1:0] read_icached_word =
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word_sel == 2'b11 ? ins_cache[31:0] :
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word_sel == 2'b10 ? ins_cache[63:32] :
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word_sel == 2'b01 ? ins_cache[95:64] :
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ins_cache[127:96];
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wire [WIDTH-1:0] read_dcached_word =
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word_sel == 2'b11 ? d_cache[31:0] :
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word_sel == 2'b10 ? d_cache[63:32] :
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word_sel == 2'b01 ? d_cache[95:64] :
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d_cache[127:96];
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(*KEEP*) assign mem_read_data = icache_hit ? read_icached_word :
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dcache_hit ? read_dcached_word :
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app_rd_data_valid ? read_word : read_buf;
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// set the write mask according to the lower bits of the address
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// (ignoring bit 0)
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assign app_wdf_mask = word_sel == 2'b11 ? 16'b1111111111110000 :
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word_sel == 2'b10 ? 16'b1111111100001111 :
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word_sel == 2'b01 ? 16'b1111000011111111 :
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16'b0000111111111111 ;
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wire write_ready = mem_write_enable & app_wdf_rdy & app_rdy;
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assign app_wdf_wren = mem_write_enable & write_ready;
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assign app_wdf_end = mem_write_enable & write_ready;
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assign app_wdf_data = { {4{mem_write_data}} };
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assign mem_wait = (dram_read_enable & ~read_inprogress) |
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(mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
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(read_inprogress & ~app_rd_data_valid);
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assign app_en = (dram_read_enable & ~read_inprogress) |
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(mem_write_enable & write_ready);
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assign app_cmd = dram_read_enable ? CMD_READ : CMD_WRITE;
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/* set instruction cache */
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always @(posedge dram_front_clk)
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begin
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if(dram_read_enable && mem_read_ins && app_rd_data_valid)
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begin
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ins_cache <= app_rd_data;
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icached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
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end
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end
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/* set data cache */
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always @(posedge dram_front_clk)
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begin
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if(dram_read_enable && !mem_read_ins && app_rd_data_valid)
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begin
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d_cache <= app_rd_data;
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dcached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
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end
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/* write-through cache - invalidate on write */
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/* invalidate data cache on write */
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// if(mem_write_enable && dcached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4])
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// dcached_addr <= {DRAM_ADDR_WIDTH-4{1'b1}};
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/* write-back cache - update cache on write */
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// write back to data cache on mem_write
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if(mem_write_enable && dcached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4])
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begin
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case(word_sel)
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2'b11: d_cache[31:0] <= mem_write_data;
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2'b10: d_cache[63:32] <= mem_write_data;
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2'b01: d_cache[95:64] <= mem_write_data;
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2'b00: d_cache[127:96] <= mem_write_data;
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endcase
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end
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end
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/* transfer read data, either from cache or from DRAM */
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always @(posedge dram_front_clk)
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begin
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if(dram_read_enable & ~read_inprogress & app_rdy)
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read_inprogress <= 1;
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if(read_inprogress & app_rd_data_valid)
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read_inprogress <= 0;
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if(dram_read_enable & app_rd_data_valid)
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read_buf <= mem_read_data;
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else
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if (mem_read_enable & icache_hit)
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read_buf <= read_icached_word;
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else
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if (mem_read_enable & dcache_hit)
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read_buf <= read_dcached_word;
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end
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endmodule
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