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mig_dram_0
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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Arty-A7-35-Master.xdc
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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bram_tdp.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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cpuclk.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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display_clock.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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dram_bridge.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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fifo.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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fifo_testbench.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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irqctrl.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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mem.v
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stdlib: start with valid random seed; other small changes
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2025-03-09 01:57:11 +01:00 |
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palette.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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sdspi.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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sdspi_testbench.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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sfifo.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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stack.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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stackcpu.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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testbench.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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top.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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uart.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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uart_tb.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
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vgafb.v
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import Vivado project, rearrange Verilog sources
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2024-09-27 22:14:57 +02:00 |
