Tridora-CPU/tridoracpu
2025-03-13 22:37:56 +01:00
..
tridoracpu.srcs tridoracpu: reduce clock speed, fix vblank flag in vgafb 2025-03-13 22:37:56 +01:00
sdspi_testbench_behav.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
testbench_behav.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
tridoracpu.xpr tridoracpu: reduce clock speed, fix vblank flag in vgafb 2025-03-13 22:37:56 +01:00