slederer ac42eec912 tridoracpu: add missing xci file for the DRAM controller		2025-03-09 23:51:22 +01:00
..
mig_a.prj	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
mig_b.prj	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
mig_dram_0.xci	tridoracpu: add missing xci file for the DRAM controller	2025-03-09 23:51:22 +01:00