83 lines
3.7 KiB
Markdown
83 lines
3.7 KiB
Markdown
# VGA Controller
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Registers
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|Name|Address|Description|
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|----|-------|-----------|
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|_FB_RA_ | $900 | Read Address |
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|_FB_WA_ | $901 | Write Address |
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| _FB_IO_ | $902 | I/O Register |
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| _FB_PS_ | $903 | Palette Select |
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| _FB_PD_ | $904 | Palette Data |
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| _FB_CTL_ | $905 | Control Register |
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## Pixel Data
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Pixel data is organized in 32-bit-words. With four bits per pixel, one word
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contains eight pixels.
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|p0 | p0 | p0 | p0 | p1 | p1 | p1 | p1 | p2 | p2 | p2 | p2 | p3 | p3 | p3 | p3 |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|p4 | p4 | p4 | p4 | p5 | p5 | p5 | p5 | p6 | 62 | p6 | p6 | p7 | p7 | p7 | p7 |
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|Bitfields|Description|
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|---------|-----------|
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| _p0_ | 4 bits color value (leftmost pixel) |
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| _p1_ | 4 bits color value |
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| _p2_ | 4 bits color value |
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| _p3_ | 4 bits color value |
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| _p4_ | 4 bits color value |
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| _p5_ | 4 bits color value |
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| _p6_ | 4 bits color value |
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| _p7_ | 4 bits color value (rightmost pixel) |
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Video memory uses a linear layout, with words using an address increment of one.
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The first word (horizontal pixel coordinates 0-3) is at address 0, the second (coordinates 4-7) at address 1 etc.
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The first line starts at address 0, the second at address 80 etc.
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To access video memory, the corresponding video memory address must be written to a latch register, then pixel data can be read or written by the I/O register. Reading and writing uses separate latch registers (the "Read Adress" and "Write Address" registers, _FB_RA_ and _FB_WA_). To read the same word and write it back, both addresses need to be set.
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Both registers have an auto-increment function. After reading the I/O register, the FB_RA register is ingremented by one. After writing to the I/O register, the FB_WA register is incremented by one.
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## Palette Data
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The VGA controller uses a 16 color palette. The palette can be changed with the FB_PS and FB_PD registers. Writing to the FB_PS register selects a palette slot. Valid values are 0-15. After a palette slot is selected, color data can be read from and written to the FB_PD register. Color data is organized as follows:
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |r |r |r |r |g |g |g |g |b |b |b |b |
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| _Bitfields_| Description |
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|------------|--------------|
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| _r_ | 4 bits red intensity |
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| _g_ | 4 bits green intensity |
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| _b_ | 4 bits blue intensity |
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The FB_PS and PB_FD registers cannot be read.
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## Control Register
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The control register contains status information. It can only be read.
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|m |m |m |m |- |- |- |- |- |- |- |- |- |- |- |- |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |vb |
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| _Bitfields_| Description |
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|------------|--------------|
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| _m_ | 4 bits mode indicator |
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| _vb_ | vertical blank |
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The _m_ field indicates the current graphics mode. At the time of writing, it is
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always 1 which denotes a 640x400x4 mode.
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The _vb_ bit is 1 when the video signal generator is in its vertical blank phase.
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