312 lines
11 KiB
Verilog
312 lines
11 KiB
Verilog
`timescale 1ns / 1ps
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// either define clock as clk (100MHz on Arty)
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// or as clk_1hz for debugging
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`define clock cpuclk
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//`define clkfreq 83333333
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`define clkfreq 76923076
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//`define clock clk
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//`define clkfreq 100000000
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//`define clock clk_1hz
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`define ENABLE_VGAFB
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`define ENABLE_MICROSD
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`define ENABLE_TDRAUDIO
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module top(
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input wire clk,
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input wire rst,
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output wire led0,
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output wire led1,
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output wire led2,
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output wire led3,
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input wire uart_txd_in,
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output wire uart_rxd_out,
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// DDR3 SDRAM
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inout wire [15:0] ddr3_dq,
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inout wire [1:0] ddr3_dqs_n,
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inout wire [1:0] ddr3_dqs_p,
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output wire [13:0] ddr3_addr,
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output wire [2:0] ddr3_ba,
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output wire ddr3_ras_n,
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output wire ddr3_cas_n,
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output wire ddr3_we_n,
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output wire ddr3_reset_n,
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output wire [0:0] ddr3_ck_p,
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output wire [0:0] ddr3_ck_n,
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output wire [0:0] ddr3_cke,
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output wire [0:0] ddr3_cs_n,
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output wire [1:0] ddr3_dm,
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output wire [0:0] ddr3_odt
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`ifdef ENABLE_VGAFB
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,
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output wire [3:0] VGA_R,
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output wire [3:0] VGA_G,
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output wire [3:0] VGA_B,
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output wire VGA_HS_O,
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output wire VGA_VS_O
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`endif
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`ifdef ENABLE_MICROSD
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,
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output wire sd_cs_n,
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output wire sd_mosi,
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input wire sd_miso,
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output wire sd_sck,
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input wire sd_cd
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`endif
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`ifdef ENABLE_TDRAUDIO
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,
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output wire amp2_ain,
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output wire amp2_gain,
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output wire amp2_shutdown_n
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`endif
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);
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reg clk_1hz;
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reg [31:0] counter;
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localparam ADDR_WIDTH = 32, WIDTH = 32,
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ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
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(* KEEP *) wire [ADDR_WIDTH-1:0] mem_addr;
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wire [WIDTH-1:0] mem_read_data;
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wire [WIDTH-1:0] mem_write_data;
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(* KEEP *) wire mem_wait;
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assign led0 = mem_wait;
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(* KEEP *) wire mem_read_enable;
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(* KEEP *) wire mem_write_enable;
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(* KEEP *) wire io_enable;
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wire [WIDTH-1:0] io_rd_data;
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wire [IOADDR_SEL-1:0] io_slot = mem_addr[IOADDR_WIDTH-1:IOADDR_WIDTH-IOADDR_SEL];
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wire irq;
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wire cpuclk, cpuclk_locked;
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wire dram_refclk200;
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wire pixclk;
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cpu_clkgen cpuclk_0(~rst, clk, cpuclk, dram_refclk200, pixclk, cpuclk_locked);
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// DRAM --------------------------------------------------------------------------
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wire [ADDR_WIDTH-1:0] dram_addr;
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wire [WIDTH-1:0] dram_read_data, dram_write_data;
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wire dram_read_enable, dram_write_enable, dram_wait;
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(* KEEP *) wire dram_read_ins;
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dram_bridge dram_bridge0 (dram_addr,
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dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,
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dram_read_ins, dram_wait,
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rst, cpuclk, dram_refclk200,
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ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
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ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
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ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke,
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ddr3_cs_n, ddr3_dm, ddr3_odt);
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mem #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(WIDTH)) mem0(
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.clk(`clock), .rst_n(rst), .addr(mem_addr),
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.data_out(mem_read_data), .read_enable(mem_read_enable),
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.data_in(mem_write_data), .write_enable(mem_write_enable),
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.io_enable(io_enable),
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.io_rd_data(io_rd_data),
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.mem_wait(mem_wait),
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.dram_addr(dram_addr),
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.dram_read_data(dram_read_data),
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.dram_write_data(dram_write_data),
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.dram_read_enable(dram_read_enable),
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.dram_write_enable(dram_write_enable),
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.dram_wait(dram_wait)
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);
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`ifdef ENABLE_VGAFB
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localparam FB_ADDR_WIDTH = 14;
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wire [FB_ADDR_WIDTH-1:0] fb_rd_addr;
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wire [FB_ADDR_WIDTH-1:0] fb_wr_addr;
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wire [WIDTH-1:0] fb_rd_data;
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wire [WIDTH-1:0] fb_wr_data;
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wire fb_rd_en, fb_wr_en;
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wire fb_cs_en = io_enable && (io_slot == 2);
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assign fb_rd_en = fb_cs_en && mem_read_enable;
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assign fb_wr_en = fb_cs_en && mem_write_enable;
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assign fb_wr_data = mem_write_data;
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vgafb vgafb0(`clock, pixclk, rst,
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mem_addr[3:0], fb_rd_data, fb_wr_data,
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fb_rd_en, fb_wr_en,
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VGA_HS_O, VGA_VS_O, VGA_R, VGA_G, VGA_B);
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`endif
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// SPI SD card controller -------------------------------------------------------------------
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`ifdef ENABLE_MICROSD
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wire [7:0] spi_tx_data;
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(*KEEP*) wire [7:0] spi_rx_data;
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wire spi_tx_ready; // ready to transmit new data
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wire spi_tx_empty; // tx fifo is empty
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wire spi_rx_avail; // a byte has been received
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wire spi_rx_ovr; // receiver overrun
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wire spi_tx_write; // write strobe
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wire spi_rx_read; // read strobe (clears rx_avail)
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wire spi_card_detect; // true is card is present
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wire spi_card_changed; // card_detect signal has changed
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wire spi_card_busy; // card is busy (MISO/DO is 0)
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wire spi_ctrl_write; // set the following flags
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wire spi_rx_filter_en; // set to wait for start bit (1-to-0) when receiving
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wire spi_txrx_en; // enable transmitter and receiver
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wire spi_sclk_f_en; // enable spi clock without transceiver
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wire spi_sclk_div_wr; // set clock divider from tx_data
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wire spi_cs; // cs signal for spi controller
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wire [WIDTH-1:0] spi_rd_data;
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assign spi_cs = io_enable && (io_slot == 1);
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// spi read data: [ 0,...,0,cd,cc,cb,tr,te,ra,ro,d,d,d,d,d,d,d,d ]
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// cd = card detect, cc = card changed, cb = card busy,
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// tr = transmitter ready, te = tx fifo empty,
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// ra = received byte available, ro = receive overrun, d = received byte
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assign spi_rd_data =
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{ {WIDTH-15{1'b0}}, spi_card_detect, spi_card_changed, spi_card_busy,
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spi_tx_ready, spi_tx_empty,
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spi_rx_avail, spi_rx_ovr, spi_rx_data };
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// spi write data: [ 0,...,0,CW,CF,Cx,Cc,Cd,DR,DW,d,d,d,d,d,d,d,d ]
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// CW = control write, CF = enable receive filter, Cx = enable transceiver,
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// Cc = force spi clock on, Cd = write clock divider,
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// DR = read acknowledge, DW = data write, d = byte to be sent
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assign spi_ctrl_write = spi_cs && mem_write_enable && mem_write_data[14];
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assign spi_rx_filter_en = mem_write_data[13];
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assign spi_txrx_en = mem_write_data[12];
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assign spi_sclk_f_en = mem_write_data[11];
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assign spi_sclk_div_wr = spi_cs && mem_write_enable && mem_write_data[10];
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assign spi_rx_read = mem_write_data[9];
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assign spi_tx_write = spi_cs && mem_write_enable && mem_write_data[8];
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assign spi_tx_data = mem_write_data[7:0];
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sdspi sdspi0(.clk(`clock), .reset(~rst),
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.tx_data(spi_tx_data), .rx_data(spi_rx_data),
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.tx_ready(spi_tx_ready), .tx_empty(spi_tx_empty),
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.rx_avail(spi_rx_avail), .rx_ovr(spi_rx_ovr),
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.tx_write(spi_tx_write), .rx_read(spi_rx_read),
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.card_detect(spi_card_detect), .card_changed(spi_card_changed), .card_busy(spi_card_busy),
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// ctrl_write is used with rx_filter_en, txrx_en and spiclk_f_en
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.ctrl_write(spi_ctrl_write),
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.rx_filter_en(spi_rx_filter_en), .txrx_en(spi_txrx_en), .spiclk_f_en(spi_sclk_f_en),
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//
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.spiclk_div_wr(spi_sclk_div_wr),
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.sd_cs_n(sd_cs_n),
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.sd_mosi(sd_mosi), .sd_miso(sd_miso), .sd_sck(sd_sck), .sd_cd(sd_cd));
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`endif
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// UART -----------------------------------------------------------------------
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// uart write data: [ 0, 0, 0, 0, 0, T, C, 0, c, c, c, c, c, c, c, c ]
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// T = transmit enable, C = receiver clear, c = 8-bit-character
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// uart read data: [ 0, 0, 0, 0, 0, 0, A, B, c, c, c, c, c, c, c, c ]
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// A = char available, B = tx busy, c = 8-bit-character
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wire uart_cs = io_enable && (io_slot == 0);
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wire uart_tx_en = uart_cs && mem_write_enable && mem_write_data[10];
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wire uart_rx_clear = uart_cs && mem_write_enable && mem_write_data[9];
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wire uart_rx_avail;
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wire uart_rx_busy, uart_tx_busy;
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wire uart_err;
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wire [7:0] uart_rx_data;
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wire [7:0] uart_tx_data;
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wire [31:0] uart_baud = 32'd115200;
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wire [WIDTH-1:0] uart_rd_data;
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assign uart_tx_data = mem_write_data[7:0];
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assign uart_rd_data = { {WIDTH-10{1'b1}}, uart_rx_avail, uart_tx_busy, uart_rx_data };
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wire audio_irq;
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buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
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uart_baud,
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uart_txd_in, uart_rxd_out,
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uart_rx_clear, uart_tx_en,
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uart_rx_avail, uart_tx_busy,
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uart_tx_data, uart_rx_data);
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// audio controller
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`ifdef ENABLE_TDRAUDIO
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wire [WIDTH-1:0] tdraudio_wr_data;
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wire [WIDTH-1:0] tdraudio_rd_data;
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wire tdraudio_rd_en, tdraudio_wr_en;
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wire tdraudio_irq;
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wire tdraudio_cs_en = io_enable && (io_slot == 4);
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assign tdraudio_rd_en = tdraudio_cs_en && mem_read_enable;
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assign tdraudio_wr_en = tdraudio_cs_en && mem_write_enable;
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assign tdraudio_wr_data = mem_write_data;
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tdraudio tdraudio0(`clock, ~rst,
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mem_addr[6:0],
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tdraudio_rd_data,
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tdraudio_wr_data,
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tdraudio_rd_en,
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tdraudio_wr_en,
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tdraudio_irq,
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amp2_ain, amp2_gain, amp2_shutdown_n);
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assign audio_irq = tdraudio_irq;
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`endif
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// interrupt controller
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reg timer_tick;
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reg[23:0] tick_count;
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wire [2:0] irq_in = { audio_irq, timer_tick, uart_rx_avail };
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wire [2:0] irqc_rd_data0;
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wire [WIDTH-1:0] irqc_rd_data = { tick_count, 5'b0, irqc_rd_data0 };
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wire irqc_seten = mem_write_data[7];
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wire irqc_cs = io_enable && (io_slot == 3);
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assign io_rd_data = (io_slot == 0) ? uart_rd_data :
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`ifdef ENABLE_MICROSD
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(io_slot == 1) ? spi_rd_data :
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`endif
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`ifdef ENABLE_VGAFB
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(io_slot == 2) ? fb_rd_data :
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`endif
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(io_slot == 3) ? irqc_rd_data:
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`ifdef ENABLE_TDRAUDIO
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(io_slot == 4) ? tdraudio_rd_data:
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`endif
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-1;
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// CPU -----------------------------------------------------------------
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stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
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.addr(mem_addr),
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.data_in(mem_read_data), .read_enable(mem_read_enable),
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.read_ins(dram_read_ins),
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.data_out(mem_write_data), .write_enable(mem_write_enable),
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.mem_wait(mem_wait),
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.debug1(led1), .debug2(led2), .debug3(led3));
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// Interrupt Controller
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irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,
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irqc_seten, irqc_rd_data0,
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irq);
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// count clock ticks
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// generate interrupt every 20nth of a second
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always @ (posedge `clock)
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begin
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counter <= counter + 1;
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if (counter >= (`clkfreq/20))
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begin
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counter <= 0;
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timer_tick <= 1;
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tick_count <= tick_count + 1'b1;
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end
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else
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begin
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timer_tick <= 0;
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end
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end
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endmodule
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