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Exact Union RegExp

slederer 4e044ad2a4 sdcardlib: use slightly faster spi clock ... also: - new benchmark results - experiment with synthesis settings		2025-09-16 21:57:53 +02:00
..
tridoracpu.srcs	tridoracpu: implement data cache	2025-09-15 23:02:22 +02:00
sdspi_testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
tridoracpu.xpr	sdcardlib: use slightly faster spi clock	2025-09-16 21:57:53 +02:00