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No commits in common. "main" and "dcache" have entirely different histories.
29 changed files with 101 additions and 1542 deletions
21
README.md
21
README.md
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@ -41,25 +41,6 @@ Other inspirations were, among others, in no particular order:
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- the Magic-1 by Bill Buzbee
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- the OPC by revaldinho
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## October 2025 Update
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This update introduces a data cache for the Tridora-CPU. It is similar to the instruction cache
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as it caches the 16 bytes coming from the DRAM memory controller. It is a write-back cache, i.e.
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when a word inside the cached area is written, it updates the cache instead of invalidating it.
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This is important because there are many idioms in the stack machine assembly language where you
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store a local variable and then read it again (e.g. updating a loop variable).
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Since for most programs, the user stack and parts of the heap are inside the DRAM area, the data cache
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has a more noticable impact. In the benchmark program that was already used for the last update,
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the data cache results in a 50% improvement for the empty loop test. This is in comparison to the version
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without data cache but with the instruction cache, both running code out of DRAM.
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It is also noticable for compile times: With the data cache, compiling and assembling the
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"hello,world" program takes 16 seconds instead of 20. With a little tweak of the SD-Card controller
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that slightly increased the data transfer rate, the build time goes down to 15 seconds.
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Also, an audio controller was added that allows interrupt-driven sample playback via an AMP2 PMOD.
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## April 2025 Update
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The clock has been reduced to 77 MHz from 83 MHz. Apparently the design was at the limit and
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timing problems were cropping up seemingly at random. Reducing the clock speed made some
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@ -81,7 +62,7 @@ on the emulator image.
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- the [Hackaday project](https://hackaday.io/project/198324-tridora-cpu) (mostly copy-paste from this README)
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- the [YouTube channel](https://www.youtube.com/@tridoracpu/videos) with some demo videos
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- the [emulator](https://git.insignificance.de/slederer/-/packages/generic/tridoraemu/0.0.5/files/12) (source and windows binary)
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- the [FPGA bitstream](https://git.insignificance.de/slederer/-/packages/generic/tdr-bitstream/0.0.4/files/16) for the Arty-A7-35T board
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- the [FPGA bitstream](https://git.insignificance.de/slederer/-/packages/generic/tdr-bitstream/0.0.2/files/14) for the Arty-A7-35T board
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- an [SD-card image](https://git.insignificance.de/slederer/-/packages/generic/tdr-cardimage/0.0.4/files/13)
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Contact the author here: tridoracpu [at] insignificance.de
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@ -9,13 +9,12 @@ The interrupt controller uses a single register at address: $980
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|t |t |t |t |t |t |t |t |- |- |- |- |- |p2 |p1 |p0 |
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|_Value_|t |t |t |t |t |t |t |t |- |- |- |- |- |- |p1 |p0 |
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|Bitfields|Description|
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|---------|-----------|
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| _t_ | unsigned 24 bit counter of timer ticks since reset
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| _p2_ | IRQ 2 (audio) interrupt pending if 1
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| _p1_ | IRQ 1 (timer tick) interrupt pending if 1
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| _p0_ | IRQ 0 (UART) interrupt pending if 1
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@ -34,4 +34,3 @@ Currently, only I/O slots 0-3 are being used.
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| 1 | $880 | SPI-SD |
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| 2 | $900 | VGA |
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| 3 | $980 | IRQC |
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| 4 | $A00 | TDRAUDIO |
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@ -103,16 +103,6 @@ Tridora-Pascal only supports the _break_ statement at the moment.
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The _exit_ statement can be used to exit the current procedure or function. If it is a function, the return value of the function is undefined if _exit_ is
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used before a return value is assigned.
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## Dynamic Memory Allocation
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Memory allocation generally works as expected with the *new* and *dispose* special procedures. The variant of *new* with two parameters that is specified in Wirth Pascal is not supported (partial allocation of a variant record). Instead, there is a variant of *new* that has a second parameter for allocating strings (see above).
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If heap allocation fails, *new* does not return and instead causes a runtime error. To avoid this, a different special procedure called *newOrNil* can be used. This procedure sets the pointer
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variable to *niL* if heap allocation fails.
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The function *MemAvail* returns the number of free bytes on the heap. It does not guarantee that this amount of memory can be allocated with *new*, because heap space can be fragmented.
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The function *MaxAvail*, which exists in some versions of Turbo Pascal and returns the size of the largest contiguous block of available heap memory, is not (yet) implemented.
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## I/O
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I/O handling in Tridora Pascal is mostly compatible with other Pascal dialects when reading/writing simple variables from/to the console. There are big differences when opening/reading/writing files explicitly.
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104
doc/tdraudio.md
104
doc/tdraudio.md
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@ -1,104 +0,0 @@
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# Audio Controller
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The audio controller provides four channels of 16-bit PCM audio playback.
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It uses multiple registers starting at address $A00.
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Each of the four channels has three registers.
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For the first channel the register addresses are:
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|Address|Description|
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|-------|-----------|
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| $A00 | Control Register |
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| $A01 | Clock Divider Register |
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| $A02 | Amplitude Register |
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The register addresses for the second channel start at $A04,
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the third channel at $A08
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and the fourth channel at $A0C.
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## Reading the control register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |-|- |- |- |- |- |- |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |- |- |i |f | e | p | c |
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|Bitfields|Description|
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|---------|-----------|
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| _i_ | interrupt is enabled for this channel when 1 |
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| _f_ | sample buffer is full when 1 |
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| _e_ | sample buffer is empty when 1 |
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| _p_ | changes from 0 to 1 and vice versa on each sample clock |
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| _c_ | channel is enabled if 1 |
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## Writing the control register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |-|- |- |- |- |- |- |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |- |- |i |- | - | - | c |
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|Bitfields|Description|
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|---------|-----------|
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| _c_ | enable channel if 1, disable if 0 |
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| _i_ | enable channel interrupt if 1, disable if 0 |
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## Writing the clock divider register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|d |d |d |d |d |d |d |d |d |d|d |d |d |d |d |d |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|d |d |d |d |d |d |d |d |d |d|d |d |d |d |d |d |
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|Bitfields|Description|
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|---------|-----------|
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| _d_ | an unsigned 32-bit value for the clock divider |
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## Writing the amplitude register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|- |- |- |- |- |- |- |- |- |-|- |- |- |- |- |- |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|a |a |a |a |a |a |a |a |a |a |a |a |a | a | a | a |
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|Bitfields|Description|
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|---------|-----------|
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| _a_ | an unsigned 16-bit value for the amplitude (sample) value with a bias of 32768 |
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## Notes
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The clock divider specifies the number of CPU clock ticks between two samples.
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Writing to the amplitude register adds the sample value to the sample buffer. The sample buffer is organized as a FIFO with 16 elements.
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Amplitude (sample) values are represented as unsigned, biased 16-bit numbers. The bias is 32768, so given an amplitude range of 1.0 to -1.0, a 1.0 is represented by 65535, 0.0 by 32768 and -1.0 by 0.
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Interrupt processing needs to be enabled for each channel if required.
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An interrupt on any channel will be signalled to the interrupt controller
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as IRQ 2. The interrupt service routine should check all running channels
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for an emtpy buffer.
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If an audio interrupt has occured on a channel, the interrupt enable flag
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is cleared for that channel. It needs to be re-enabled in the interrupt service routine.
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Interrupts also need to be enabled on the interrupt controller,
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and re-enabled there after each interrupt.
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@ -97,7 +97,7 @@ Running benchmarks.prog
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Arty-A7-35T
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76.92MHz, 64KB SRAM, 256MB DRAM,
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16B instruction cache, 16B wt data cache
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running in SRAM
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running in DRAM (except corelib, stdlib, runtime)
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Running benchmarks.prog
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empty loop 10M 00:00:07
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@ -124,7 +124,7 @@ Running benchmarks.prog
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Arty-A7-35T
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76.92MHz, 64KB SRAM, 256MB DRAM,
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16B instruction cache, 16B wb data cache
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running in SRAM
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running in DRAM (except corelib, stdlib, runtime)
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Running benchmarks.prog
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empty loop 10M 00:00:04
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@ -149,7 +149,7 @@ Running benchmarks.prog
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Arty-A7-35T
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76.92MHz, 32KB SRAM, 256MB DRAM,
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16B instruction cache, 16B wb data cache
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running in SRAM
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running in DRAM (except corelib, stdlib, runtime)
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Running benchmarks.prog
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empty loop 10M 00:00:04
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@ -169,28 +169,3 @@ Running benchmarks.prog
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array copy 128k 1K 00:00:39
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exp() 10K 00:00:25
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cos() 10K 00:00:05
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--------------------------------------------
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Arty-A7-35T
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76.92MHz, 64KB SRAM, 256MB DRAM,
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16B instruction cache, 16B wb data cache
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running in DRAM (except corelib, stdlib, runtime)
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Running benchmarks.prog
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empty loop 10M 00:00:10
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write variable 10M 00:00:11
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read variable 10M 00:00:11
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integer addition 10M 00:00:13
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real addition 1M 00:00:27
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integer multiplication 1M 00:00:35
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real multiplication 1M 00:00:43
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integer division 1M 00:01:05
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real division 1M 00:00:51
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string indexing 1M 00:00:36
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string iteration 1M 00:00:20
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new/dispose 1k 1M 00:00:23
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new/dispose 128k 1M 00:00:23
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array copy 1k 10K 00:00:03
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array copy 128k 1K 00:00:48
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exp() 10K 00:00:28
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cos() 10K 00:00:04
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@ -1,5 +0,0 @@
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const FIREWIDTH = 319; FIREHEIGHT = 79; (* keep in sync with fastfire.s! *)
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type FireBuf = array [0..FIREHEIGHT, 0..FIREWIDTH] of integer;
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procedure FastFireUpdate(var f:FireBuf); external;
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procedure FastFireDraw(var f:FireBuf;screenx, screeny:integer); external;
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@ -1,326 +0,0 @@
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; width and height of the fire cell matrix
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; Be sure to sync this with fastfire.inc!
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.EQU FIREWIDTH 319
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.EQU FIREHEIGHT 79
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;
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; The cell matrix actually has one column
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; and one row more than FIREWIDTH and
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; FIREHEIGHT to handle the negative
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; X offsets when calculating new
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; cell values.
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; Likewise, there is one more row.
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; So rows are processed from 0 to FIREHEIGHT - 2
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; and columms from 1 to FIREWIDTH - 1.
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; cells considered for calculating new
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; value for cell O (reference cells):
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; .....O......
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; ....123.....
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; .....4......
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; args: pointer to fire cell buffer
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.EQU FF_ROW_COUNT 0
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.EQU FF_COL_COUNT 4
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.EQU FF_ROW_OFFS 8
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.EQU FF_OFFS1 12
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.EQU FF_OFFS2 16
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.EQU FF_OFFS3 20
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.EQU FF_OFFS4 24
|
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.EQU FF_CELL_PTR 28
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.EQU FF_FS 32
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FASTFIREUPDATE:
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FPADJ -FF_FS
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STORE FF_CELL_PTR
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LOADC FIREHEIGHT-1
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STORE FF_ROW_COUNT
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|
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; calculate offsets for reference cells
|
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LOADC FIREWIDTH+1
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SHL 2
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DUP
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STORE FF_ROW_OFFS ; offset to next row: WIDTH*4
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DEC 4 ; offset to cell 1: row offset - 4
|
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DUP
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STORE FF_OFFS1
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INC 4
|
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DUP
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STORE FF_OFFS2 ; offset to cell 2: + 4
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INC 4
|
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STORE FF_OFFS3 ; offset to cell 3: + 4
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LOAD FF_ROW_OFFS
|
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SHL 1 ; offset to cell 4: row offset * 2
|
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STORE FF_OFFS4
|
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|
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; start at column 1
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LOAD FF_CELL_PTR
|
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INC 4
|
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STORE FF_CELL_PTR
|
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FF_ROW:
|
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LOADC FIREWIDTH-1
|
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STORE FF_COL_COUNT
|
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|
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FF_COL:
|
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LOAD FF_CELL_PTR
|
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LOAD FF_OFFS1
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ADD
|
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LOADI
|
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|
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LOAD FF_CELL_PTR
|
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LOAD FF_OFFS2
|
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ADD
|
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LOADI
|
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|
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LOAD FF_CELL_PTR
|
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LOAD FF_OFFS3
|
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ADD
|
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LOADI
|
||||
|
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LOAD FF_CELL_PTR
|
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LOAD FF_OFFS4
|
||||
ADD
|
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LOADI
|
||||
|
||||
ADD
|
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ADD
|
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ADD
|
||||
|
||||
SHR
|
||||
SHR
|
||||
|
||||
; if new cell value > 0, subtract 1 to cool down
|
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DUP
|
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CBRANCH.Z FF_SKIP
|
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DEC 1
|
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FF_SKIP:
|
||||
LOAD FF_CELL_PTR ; load cell ptr
|
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SWAP ; swap with new value
|
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STOREI 4 ; store with postincrement
|
||||
STORE FF_CELL_PTR ; save new ptr value
|
||||
|
||||
LOAD FF_COL_COUNT ; decrement column count
|
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DEC 1
|
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DUP
|
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STORE FF_COL_COUNT
|
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CBRANCH.NZ FF_COL ; loop if col count <> 0
|
||||
|
||||
; at the end of a row, go to next row
|
||||
; by adding 8 to the cell pointer,
|
||||
; skipping the first cell of the next row
|
||||
LOAD FF_CELL_PTR
|
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INC 8
|
||||
STORE FF_CELL_PTR
|
||||
|
||||
LOAD FF_ROW_COUNT ; decrement row count
|
||||
DEC 1
|
||||
DUP
|
||||
STORE FF_ROW_COUNT
|
||||
CBRANCH.NZ FF_ROW ; loop if row count <> 0
|
||||
|
||||
FF_EXIT:
|
||||
FPADJ FF_FS
|
||||
RET
|
||||
|
||||
; framebuffer controller registers
|
||||
.EQU FB_RA $900
|
||||
.EQU FB_WA $901
|
||||
.EQU FB_IO $902
|
||||
.EQU FB_PS $903
|
||||
.EQU FB_PD $904
|
||||
.EQU FB_CTL $905
|
||||
.EQU WORDS_PER_LINE 80
|
||||
|
||||
; fire width in vmem words (strict left-to-right evaluation)
|
||||
.EQU FFD_ROW_WORDS 1 + FIREWIDTH / 8
|
||||
|
||||
; draw all fire cells
|
||||
; args: pointer to fire cell buffer, screen x, screen y
|
||||
.EQU FFD_CELL_PTR 0
|
||||
.EQU FFD_X 4
|
||||
.EQU FFD_Y 8
|
||||
.EQU FFD_ROW_COUNT 12
|
||||
.EQU FFD_ROW_WORDCOUNT 16
|
||||
.EQU FFD_VMEM_PTR 20
|
||||
.EQU FFD_FS 24
|
||||
FASTFIREDRAW:
|
||||
FPADJ -FFD_FS
|
||||
STORE FFD_Y
|
||||
STORE FFD_X
|
||||
STORE FFD_CELL_PTR
|
||||
|
||||
; calculate video memory addr
|
||||
; addr = y * 80 + X / 8
|
||||
LOAD FFD_Y
|
||||
SHL 2 ; y * 16
|
||||
SHL 2
|
||||
DUP
|
||||
SHL 2 ; + y * 64
|
||||
ADD ; = y * 80
|
||||
|
||||
LOAD FFD_X
|
||||
SHR
|
||||
SHR
|
||||
SHR
|
||||
ADD ; + x / 8
|
||||
|
||||
DUP
|
||||
STORE FFD_VMEM_PTR
|
||||
LOADC FB_WA ; set vmem write address
|
||||
SWAP
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
LOADC FIREHEIGHT + 1
|
||||
STORE FFD_ROW_COUNT
|
||||
FFD_ROW:
|
||||
LOADC FFD_ROW_WORDS
|
||||
STORE FFD_ROW_WORDCOUNT
|
||||
|
||||
LOADC FB_WA ; set vmem write address
|
||||
LOAD FFD_VMEM_PTR
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
FFD_WORD:
|
||||
LOAD FFD_CELL_PTR ; load cell ptr
|
||||
LOADC 0 ; vmem word, start with 0
|
||||
|
||||
; leftmost pixel (0)
|
||||
OVER ; [ cptr, vmemw, cptr ]
|
||||
LOADI ; load cell value [ cptr, vmemw, cellval ]
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR ; [ cptr, vmemw, cellval shr 3 ]
|
||||
OR ; [ cptr, vmemw ]
|
||||
SWAP ; [ vmemw, cptr ]
|
||||
INC 4 ; increment cell ptr on stack [ vmemw, cptr + 4 ]
|
||||
SWAP ; [ cptr + 4, vmemw ]
|
||||
|
||||
SHL 2 ; move bits to left for next pixel
|
||||
SHL 2
|
||||
|
||||
; pixel 1
|
||||
OVER
|
||||
LOADI ; load cell value
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR
|
||||
OR
|
||||
SWAP
|
||||
INC 4 ; increment cell ptr on stack
|
||||
SWAP
|
||||
|
||||
SHL 2 ; move bits to left for next pixel
|
||||
SHL 2
|
||||
|
||||
; pixel 2
|
||||
OVER
|
||||
LOADI ; load cell value
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR
|
||||
OR
|
||||
SWAP
|
||||
INC 4 ; increment cell ptr on stack
|
||||
SWAP
|
||||
|
||||
SHL 2 ; move bits to left for next pixel
|
||||
SHL 2
|
||||
|
||||
; pixel 3
|
||||
OVER
|
||||
LOADI ; load cell value
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR
|
||||
OR
|
||||
SWAP
|
||||
INC 4 ; increment cell ptr on stack
|
||||
SWAP
|
||||
|
||||
SHL 2 ; move bits to left for next pixel
|
||||
SHL 2
|
||||
|
||||
; pixel 4
|
||||
OVER
|
||||
LOADI ; load cell value
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR
|
||||
OR
|
||||
SWAP
|
||||
INC 4 ; increment cell ptr on stack
|
||||
SWAP
|
||||
|
||||
SHL 2 ; move bits to left for next pixel
|
||||
SHL 2
|
||||
|
||||
; pixel 5
|
||||
OVER
|
||||
LOADI ; load cell value
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR
|
||||
OR
|
||||
SWAP
|
||||
INC 4 ; increment cell ptr on stack
|
||||
SWAP
|
||||
|
||||
SHL 2 ; move bits to left for next pixel
|
||||
SHL 2
|
||||
|
||||
; pixel 6
|
||||
OVER
|
||||
LOADI ; load cell value
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR
|
||||
OR
|
||||
SWAP
|
||||
INC 4 ; increment cell ptr on stack
|
||||
SWAP
|
||||
|
||||
SHL 2 ; move bits to left for next pixel
|
||||
SHL 2
|
||||
|
||||
; pixel 7
|
||||
OVER
|
||||
LOADI ; load cell value
|
||||
SHR ; scale it down (from 7 bits to 4)
|
||||
SHR
|
||||
SHR
|
||||
OR
|
||||
SWAP
|
||||
INC 4 ; increment cell ptr on stack
|
||||
SWAP
|
||||
|
||||
; store word to vmem
|
||||
; vmem write addr will autoincrement
|
||||
LOADC FB_IO
|
||||
SWAP
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
STORE FFD_CELL_PTR
|
||||
|
||||
; prepare for next word
|
||||
LOAD FFD_ROW_WORDCOUNT
|
||||
DEC 1
|
||||
DUP
|
||||
STORE FFD_ROW_WORDCOUNT
|
||||
CBRANCH.NZ FFD_WORD
|
||||
|
||||
; prepare for next row
|
||||
LOAD FFD_VMEM_PTR
|
||||
LOADC WORDS_PER_LINE
|
||||
ADD
|
||||
STORE FFD_VMEM_PTR
|
||||
|
||||
LOAD FFD_ROW_COUNT
|
||||
DEC 1
|
||||
DUP
|
||||
STORE FFD_ROW_COUNT
|
||||
CBRANCH.NZ FFD_ROW
|
||||
FFD_EXIT:
|
||||
FPADJ FFD_FS
|
||||
RET
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
{$H1}
|
||||
{$S2}
|
||||
program fire;
|
||||
const MAXX = 30;
|
||||
MAXY = 50;
|
||||
var firebuf: array [0..MAXY, 0..MAXX] of integer;
|
||||
|
||||
firepalette: array [0..15] of integer =
|
||||
( $FFA, $FF8, $FF4, $FF0, $FE0, $FD0, $FA0, $F90,
|
||||
$F00, $E00, $D00, $A00, $800, $600, $300, $000);
|
||||
x,y:integer;
|
||||
|
||||
procedure createPalette;
|
||||
var i:integer;
|
||||
begin
|
||||
for i := 15 downto 0 do
|
||||
setpalette(15 - i, firepalette[i]);
|
||||
end;
|
||||
|
||||
procedure fireItUp;
|
||||
var x,y:integer;
|
||||
begin
|
||||
y := MAXY - 1;
|
||||
for x := 1 to MAXX - 1 do
|
||||
firebuf[y, x] := random and 127;
|
||||
end;
|
||||
|
||||
procedure updateFire;
|
||||
var i,x,y:integer;
|
||||
begin
|
||||
for y := 0 to MAXY - 2 do
|
||||
for x := 1 to MAXX - 1 do
|
||||
begin
|
||||
i :=
|
||||
((firebuf[y + 1, x - 1]
|
||||
+ firebuf[y + 1, x]
|
||||
+ firebuf[y + 1, x + 1]
|
||||
+ firebuf[y + 2, x])
|
||||
) shr 2;
|
||||
if i > 0 then
|
||||
i := i - 1;
|
||||
firebuf[y, x] := i;
|
||||
end;
|
||||
end;
|
||||
|
||||
procedure drawFire;
|
||||
var x, y, col:integer;
|
||||
begin
|
||||
for y := 0 to MAXY - 1 do
|
||||
begin
|
||||
x := 0;
|
||||
for col in firebuf[y] do
|
||||
begin
|
||||
putpixel(300 + x, 150 + y, col shr 3);
|
||||
x := x + 1;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
begin
|
||||
randomize;
|
||||
initgraphics;
|
||||
createPalette;
|
||||
while not conavail do
|
||||
begin
|
||||
fireItUp;
|
||||
updateFire;
|
||||
drawFire;
|
||||
end;
|
||||
|
||||
for y := 0 to MAXY do
|
||||
begin
|
||||
x := firebuf[y, 10];
|
||||
drawline(0, y, x, y, 1);
|
||||
end;
|
||||
end.
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
{$H1}
|
||||
{$S1}
|
||||
program fire2;
|
||||
uses fastfire;
|
||||
|
||||
const MAXX = FIREWIDTH;
|
||||
MAXY = FIREHEIGHT;
|
||||
|
||||
var firecells: FireBuf;
|
||||
|
||||
firepalette: array [0..15] of integer =
|
||||
{ ( $FFA, $FF8, $FF4, $FF0, $FE0, $FD0, $FA0, $F90,
|
||||
$F00, $E00, $D00, $A00, $800, $600, $300, $000); }
|
||||
( $FFA, $FFA, $FFA, $FFA, $FF0, $FF0, $FF0, $FF0,
|
||||
$FF0, $FD0, $FA0, $C00, $A00, $700, $400, $000);
|
||||
x,y:integer;
|
||||
|
||||
procedure createPalette;
|
||||
var i:integer;
|
||||
begin
|
||||
for i := 15 downto 0 do
|
||||
setpalette(15 - i, firepalette[i]);
|
||||
end;
|
||||
|
||||
procedure fireItUp;
|
||||
var x,y:integer;
|
||||
begin
|
||||
y := MAXY - 1;
|
||||
for x := 1 to MAXX - 1 do
|
||||
firecells[y, x] := random and 127;
|
||||
end;
|
||||
|
||||
|
||||
procedure updateFire;
|
||||
var i,x,y:integer;
|
||||
begin
|
||||
for y := 0 to MAXY - 2 do
|
||||
for x := 1 to MAXX - 1 do
|
||||
begin
|
||||
i :=
|
||||
((firecells[y + 1, x - 1]
|
||||
+ firecells[y + 1, x]
|
||||
+ firecells[y + 1, x + 1]
|
||||
+ firecells[y + 2, x])
|
||||
) shr 2;
|
||||
if i > 0 then
|
||||
i := i - 1;
|
||||
firecells[y, x] := i;
|
||||
end;
|
||||
end;
|
||||
|
||||
procedure drawFire;
|
||||
var x, y, col:integer;
|
||||
begin
|
||||
for y := 0 to MAXY - 1 do
|
||||
begin
|
||||
x := 0;
|
||||
for col in firecells[y] do
|
||||
begin
|
||||
putpixel(100 + x, 150 + y, col shr 3);
|
||||
x := x + 1;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
begin
|
||||
randomize;
|
||||
initgraphics;
|
||||
createPalette;
|
||||
while not conavail do
|
||||
begin
|
||||
fireItUp;
|
||||
FastFireUpdate(firecells);
|
||||
{ updateFire; }
|
||||
FastFireDraw(firecells, 160, 100);
|
||||
{ drawFire; }
|
||||
end;
|
||||
|
||||
for y := 0 to MAXY do
|
||||
begin
|
||||
x := firecells[y, 10];
|
||||
drawline(0, y, x, y, 1);
|
||||
end;
|
||||
end.
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
{$H1536}
|
||||
program pcmtest;
|
||||
uses pcmaudio;
|
||||
|
||||
var filename:string;
|
||||
buf:SndBufPtr;
|
||||
f:file;
|
||||
size:integer;
|
||||
i:integer;
|
||||
c:char;
|
||||
sampleRate:integer;
|
||||
err:integer;
|
||||
begin
|
||||
if ParamCount > 0 then
|
||||
filename := ParamStr(1)
|
||||
else
|
||||
begin
|
||||
write('Filename> ');
|
||||
readln(filename);
|
||||
end;
|
||||
|
||||
err := 1;
|
||||
if ParamCount > 1 then
|
||||
val(ParamStr(2),sampleRate, err);
|
||||
|
||||
if err <> 0 then
|
||||
sampleRate := 16000;
|
||||
|
||||
open(f, filename, ModeReadOnly);
|
||||
size := FileSize(f);
|
||||
new(buf, size);
|
||||
|
||||
buf^ := '';
|
||||
write('Reading ', size, ' bytes...');
|
||||
for i := 1 to size do
|
||||
begin
|
||||
read(f,c);
|
||||
AppendChar(buf^,c);
|
||||
end;
|
||||
writeln;
|
||||
|
||||
close(f);
|
||||
|
||||
PlaySample(buf, sampleRate);
|
||||
|
||||
dispose(buf);
|
||||
end.
|
||||
|
|
@ -1,74 +0,0 @@
|
|||
{$H2560}
|
||||
program pcmtest2;
|
||||
uses pcmaudio;
|
||||
|
||||
var filename:string;
|
||||
buf:SndBufPtr;
|
||||
sampleRate:integer;
|
||||
err:integer;
|
||||
done:boolean;
|
||||
c:char;
|
||||
|
||||
function readAudioFile(fname:string):SndBufPtr;
|
||||
var i,size:integer;
|
||||
c:char;
|
||||
buf:SndBufPtr;
|
||||
f:file;
|
||||
begin
|
||||
open(f, fname, ModeReadOnly);
|
||||
size := FileSize(f);
|
||||
new(buf, size);
|
||||
|
||||
buf^ := '';
|
||||
write('Reading ', size, ' bytes...');
|
||||
for i := 1 to size do
|
||||
begin
|
||||
read(f,c);
|
||||
AppendChar(buf^,c);
|
||||
end;
|
||||
writeln;
|
||||
|
||||
close(f);
|
||||
|
||||
readAudioFile := buf;
|
||||
end;
|
||||
|
||||
begin
|
||||
if ParamCount > 0 then
|
||||
filename := ParamStr(1)
|
||||
else
|
||||
begin
|
||||
write('Filename> ');
|
||||
readln(filename);
|
||||
end;
|
||||
|
||||
err := 1;
|
||||
if ParamCount > 1 then
|
||||
val(ParamStr(2), sampleRate, err);
|
||||
if err > 0 then
|
||||
sampleRate := 32000;
|
||||
|
||||
buf := readAudioFile(filename);
|
||||
|
||||
SampleQStart(buf, sampleRate);
|
||||
|
||||
write('Press ESC to stop> ');
|
||||
done := false;
|
||||
while not done do
|
||||
begin
|
||||
read(c);
|
||||
if c = #27 then
|
||||
begin
|
||||
done := true; writeln(';');
|
||||
end
|
||||
else
|
||||
if c = '?' then
|
||||
begin
|
||||
writeln; writeln('Queue: ', SampleQSize);
|
||||
end;
|
||||
end;
|
||||
|
||||
SampleQStop;
|
||||
|
||||
dispose(buf);
|
||||
end.
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
type SndBuf = string[32768];
|
||||
type SndBufPtr = ^SndBuf;
|
||||
|
||||
procedure PlaySample(buf:SndBufPtr;sampleRate:integer); external;
|
||||
procedure SampleQStart(buf:SndBufPtr;sampleRate:integer); external;
|
||||
procedure SampleQStop; external;
|
||||
function SampleQSize:integer; external;
|
||||
247
lib/pcmaudio.s
247
lib/pcmaudio.s
|
|
@ -1,247 +0,0 @@
|
|||
.EQU AUDIO_BASE $A00
|
||||
.EQU IRQC_REG $980
|
||||
.EQU IRQC_EN $80
|
||||
|
||||
; args: sample rate
|
||||
START_PCMAUDIO:
|
||||
; calculate clock divider
|
||||
LOADCP 77000000
|
||||
SWAP
|
||||
LOADCP _DIV
|
||||
CALL
|
||||
|
||||
LOADC AUDIO_BASE + 1
|
||||
SWAP ; put clock divider on ToS
|
||||
; LOADCP 4812 ; clock divider for 16KHz sample rate
|
||||
; LOADCP 2406 ; clock divider for 32KHz sample rate
|
||||
STOREI 1
|
||||
LOADCP 32768 ; set amplitude to biased 0
|
||||
STOREI
|
||||
DROP
|
||||
LOADC AUDIO_BASE
|
||||
LOADC 17 ; enable channel, enable interrupt
|
||||
STOREI
|
||||
DROP
|
||||
RET
|
||||
|
||||
STOP_AUDIO:
|
||||
LOADC AUDIO_BASE
|
||||
LOADC 0
|
||||
STOREI
|
||||
DROP
|
||||
RET
|
||||
|
||||
; args: pointer to pascal string, sample rate
|
||||
.EQU PS_PTR 0
|
||||
.EQU PS_COUNT 4
|
||||
.EQU PS_FS 12
|
||||
PLAYSAMPLE:
|
||||
FPADJ -PS_FS
|
||||
|
||||
LOADCP START_PCMAUDIO
|
||||
CALL
|
||||
|
||||
DUP
|
||||
LOADI ; get string size from header
|
||||
SHR ; divide by 4 to get word count
|
||||
SHR
|
||||
|
||||
STORE PS_COUNT
|
||||
INC 8 ; skip rest of header
|
||||
STORE PS_PTR ; store sample data pointer
|
||||
|
||||
PS_L0:
|
||||
LOAD PS_PTR ; load pointer
|
||||
INC.S1.X2Y 4 ; increment and keep old value
|
||||
STORE PS_PTR ; store incremented value
|
||||
|
||||
LOADI ; load 32 bit word
|
||||
DUP
|
||||
BROT ; get upper 16 bit word
|
||||
BROT
|
||||
LOADCP $FFFF
|
||||
AND
|
||||
|
||||
LOADCP PLAY_1SAMPLE
|
||||
CALL
|
||||
|
||||
LOADCP $FFFF ; get lower 16 bit word
|
||||
AND
|
||||
LOADCP PLAY_1SAMPLE
|
||||
CALL
|
||||
|
||||
LOAD PS_COUNT ; load word count
|
||||
DEC 1 ; decrement
|
||||
DUP
|
||||
STORE PS_COUNT
|
||||
CBRANCH.NZ PS_L0 ; loop if not zero
|
||||
|
||||
LOADCP STOP_AUDIO
|
||||
CALL
|
||||
|
||||
FPADJ PS_FS
|
||||
RET
|
||||
|
||||
; play one sample, waiting
|
||||
; for the clock divider, which
|
||||
; is visible via the phase flag
|
||||
; args: 16-bit unsigned sample
|
||||
PLAY_1SAMPLE:
|
||||
|
||||
PLAY1_L0:
|
||||
LOADC AUDIO_BASE
|
||||
LOADI
|
||||
LOADC 8 ; get fifo_full flag
|
||||
AND
|
||||
CBRANCH.NZ PLAY1_L0 ; loop if fifo is full
|
||||
|
||||
LOADC AUDIO_BASE+2 ; store amplitude value
|
||||
SWAP
|
||||
STOREI
|
||||
DROP
|
||||
RET
|
||||
|
||||
; start interrupt-driven sample playback
|
||||
; args: pointer to pascal string, sample rate
|
||||
SAMPLEQSTART:
|
||||
LOADCP START_PCMAUDIO
|
||||
CALL
|
||||
|
||||
LOADCP SMPLQ_COUNT
|
||||
OVER
|
||||
LOADI ; get string size from header
|
||||
SHR ; divide by 4 to get word count
|
||||
SHR
|
||||
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
LOADCP SMPLQ_PTR
|
||||
SWAP
|
||||
INC 8 ; skip rest of header
|
||||
STOREI ; store sample data pointer
|
||||
DROP
|
||||
|
||||
LOADCP SMPLQ_ISR ; set interrupt handler
|
||||
STOREREG IV
|
||||
|
||||
LOADC IRQC_REG ; enable irq
|
||||
LOADC IRQC_EN
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
RET
|
||||
|
||||
SAMPLEQSTOP:
|
||||
LOADCP SMPLQ_PTR
|
||||
LOADC 0
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
LOADCP STOP_AUDIO
|
||||
CALL
|
||||
|
||||
LOADC IRQC_REG ; disable irq
|
||||
LOADC 0
|
||||
STOREI
|
||||
DROP
|
||||
RET
|
||||
|
||||
SAMPLEQSIZE:
|
||||
LOADCP SMPLQ_COUNT
|
||||
LOADI
|
||||
RET
|
||||
|
||||
SMPLQ_PTR: .WORD 0
|
||||
SMPLQ_COUNT: .WORD 0
|
||||
|
||||
SMPLQ_ISR:
|
||||
LOADC IRQC_REG
|
||||
LOADI
|
||||
LOADC 4 ; check for audio interrupt
|
||||
AND
|
||||
CBRANCH.Z SMPLQ_I_XT ; if flag not set, exit
|
||||
|
||||
SMPLQ_I_L:
|
||||
LOADCP SMPLQ_PTR
|
||||
LOADI ; load word pointer
|
||||
DUP
|
||||
CBRANCH.NZ SMPLQ_I_B ; check for null pointer
|
||||
DROP
|
||||
BRANCH SMPLQ_I_XT ; if null, end interrupt routine
|
||||
SMPLQ_I_B:
|
||||
LOADI ; load next word
|
||||
DUP
|
||||
|
||||
BROT ; get high half-word
|
||||
BROT
|
||||
LOADCP $FFFF
|
||||
AND
|
||||
|
||||
LOADC AUDIO_BASE+2
|
||||
SWAP
|
||||
STOREI ; write sample, keep addr
|
||||
|
||||
SWAP ; addr to NoS, lower halfword on ToS
|
||||
LOADCP $FFFF
|
||||
AND
|
||||
STOREI ; write sample
|
||||
DROP
|
||||
|
||||
; decrement word count
|
||||
LOADCP SMPLQ_COUNT
|
||||
LOADI.S1.X2Y ; load counter, keep addr
|
||||
DEC 1
|
||||
DUP
|
||||
CBRANCH.Z SMPLQ_I_END ; end if zero
|
||||
|
||||
STOREI ; store new counter value
|
||||
DROP
|
||||
|
||||
; increment pointer
|
||||
LOADCP SMPLQ_PTR
|
||||
LOADI.S1.X2Y
|
||||
INC 4
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
; check if fifo is full
|
||||
LOADC AUDIO_BASE
|
||||
LOADI
|
||||
LOADC 8 ; fifo_full
|
||||
AND
|
||||
CBRANCH.Z SMPLQ_I_L ; next sample if not full
|
||||
|
||||
LOADC AUDIO_BASE
|
||||
LOADC 17 ; re-enable channel interrupt
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
BRANCH SMPLQ_I_XT
|
||||
|
||||
; end playback, set ptr and counter to zero
|
||||
SMPLQ_I_END:
|
||||
DROP
|
||||
DROP
|
||||
LOADCP SMPLQ_PTR
|
||||
LOADC 0
|
||||
STOREI
|
||||
DROP
|
||||
LOADCP SMPLQ_COUNT
|
||||
LOADC 0
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
; set amplitude out to zero (biased)
|
||||
LOADC AUDIO_BASE+2
|
||||
LOADCP 32768
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
SMPLQ_I_XT:
|
||||
LOADC IRQC_REG ; re-enable interrupts
|
||||
LOADC IRQC_EN
|
||||
STOREI
|
||||
DROP
|
||||
LOADREG IR ; jump via interrupt return register
|
||||
JUMP
|
||||
|
|
@ -1931,12 +1931,6 @@ _CLEARESTACK_XT:
|
|||
; Terminate program: clear estack and
|
||||
; jump to coreloader
|
||||
PTERM:
|
||||
; just to be safe, disable interrupts
|
||||
LOADC $980
|
||||
LOADC 0
|
||||
STOREI
|
||||
DROP
|
||||
|
||||
LOADCP _CLEARESTACK
|
||||
CALL
|
||||
LOADCP LOADER_START
|
||||
|
|
|
|||
|
|
@ -1844,8 +1844,6 @@ end;
|
|||
|
||||
function filesize(var fil:file):integer;
|
||||
begin
|
||||
checkerror(fil);
|
||||
|
||||
if fil.typ = IOChannel then
|
||||
filesize := -1
|
||||
else
|
||||
|
|
|
|||
|
|
@ -324,9 +324,7 @@ begin
|
|||
rewindStringList(usedUnits);
|
||||
while nextStringListItem(usedUnits, unitName) do
|
||||
emitInclude(unitName + UnitSuffix2);
|
||||
(* _END label needs to be word-aligned because
|
||||
it is used as the start of the heap *)
|
||||
emitIns('.ALIGN');
|
||||
|
||||
emitLabelRaw('_END');
|
||||
end;
|
||||
|
||||
|
|
|
|||
|
|
@ -2056,9 +2056,6 @@ begin
|
|||
operandValue := 0;
|
||||
emitBlock(count, operandValue);
|
||||
end
|
||||
else
|
||||
if lastToken.tokenText = '.ALIGN' then
|
||||
alignOutput(wordSize)
|
||||
else
|
||||
errorExit2('Unrecognized directive', lastToken.tokenText);
|
||||
end;
|
||||
|
|
|
|||
|
|
@ -226,7 +226,6 @@ begin
|
|||
if not invalid then
|
||||
begin
|
||||
open(xferFile, filename, ModeOverwrite);
|
||||
blockNo := 0;
|
||||
done := false;
|
||||
repeat
|
||||
serReadBlock(ok);
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
|
|||
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
|
||||
|
||||
## Switches
|
||||
#set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0]
|
||||
#set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports sw1]
|
||||
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0]
|
||||
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports sw1]
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
|
||||
|
||||
|
|
@ -34,7 +34,7 @@ set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports led2]
|
|||
set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports led3]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0]
|
||||
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0]
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn1 }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
|
||||
|
|
@ -70,10 +70,10 @@ set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports VGA_VS_O]
|
|||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
|
||||
|
||||
## Pmod Header JD
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { amp2_ain }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
|
||||
set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { amp2_gain }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
|
||||
set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { amp2_shutdown_n }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
|
|||
assign app_wdf_data = { {4{mem_write_data}} };
|
||||
|
||||
assign mem_wait = (dram_read_enable & ~read_inprogress) |
|
||||
(mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
|
||||
(mem_write_enable & ~dcache_hit & (~app_wdf_rdy | ~app_rdy)) |
|
||||
(read_inprogress & ~app_rd_data_valid);
|
||||
|
||||
assign app_en = (dram_read_enable & ~read_inprogress) |
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module irqctrl #(IRQ_LINES = 3, IRQ_DELAY_WIDTH = 4) (
|
||||
module irqctrl #(IRQ_LINES = 2, IRQ_DELAY_WIDTH = 4) (
|
||||
input wire clk,
|
||||
input wire [IRQ_LINES-1:0] irq_in,
|
||||
input wire cs,
|
||||
|
|
|
|||
|
|
@ -16,9 +16,9 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
|
|||
output wire write_enable,
|
||||
input wire mem_wait,
|
||||
|
||||
output wire debug1,
|
||||
output wire debug2,
|
||||
output wire debug3
|
||||
output wire led1,
|
||||
output wire led2,
|
||||
output wire led3
|
||||
);
|
||||
|
||||
localparam EVAL_STACK_INDEX_WIDTH = 6;
|
||||
|
|
@ -90,6 +90,7 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
|
|||
wire mem_write;
|
||||
|
||||
wire x_is_zero;
|
||||
// wire [WIDTH-1:0] y_plus_operand = Y + operand;
|
||||
|
||||
wire x_equals_y = X == Y;
|
||||
wire y_lessthan_x = $signed(Y) < $signed(X);
|
||||
|
|
@ -104,10 +105,16 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
|
|||
assign write_enable = mem_write_enable;
|
||||
|
||||
// debug output ------------------------------------------------------------------------------------
|
||||
assign debug1 = reset;
|
||||
assign debug2 = ins_loadc;
|
||||
assign debug3 = ins_branch;
|
||||
|
||||
assign led1 = reset;
|
||||
assign led2 = ins_loadc;
|
||||
assign led3 = ins_branch;
|
||||
// assign debug_out1 = { mem_read_enable, mem_write_enable, x_is_zero,
|
||||
// ins_branch, ins_aluop, y_lessthan_x, x_equals_y, {7{1'b0}}, seq_state};
|
||||
// assign debug_out2 = data_in;
|
||||
// assign debug_out3 = nX;
|
||||
// assign debug_out4 = nPC;
|
||||
// assign debug_out5 = ins;
|
||||
// assign debug_out6 = IV;
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
// instruction decoding
|
||||
|
|
|
|||
|
|
@ -1,270 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
// waveform generator module (PCM)
|
||||
module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
|
||||
AMP_WIDTH=16, AMP_BIAS=32768) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire [1:0] reg_sel,
|
||||
output wire [DATA_WIDTH-1:0] rd_data,
|
||||
input wire [AMP_WIDTH-1:0] wr_data,
|
||||
input wire rd_en,
|
||||
input wire wr_en,
|
||||
|
||||
output wire [AMP_WIDTH-1:0] amp_val,
|
||||
output wire running,
|
||||
output wire irq
|
||||
);
|
||||
|
||||
localparam TDRAU_REG_CTL = 0; /* control register */
|
||||
localparam TDRAU_REG_CLK = 1; /* clock divider register */
|
||||
localparam TDRAU_REG_AMP = 2; /* amplitude (volume) register */
|
||||
|
||||
/* avoid warning about unconnected port */
|
||||
(* keep="soft" *) wire _unused = rd_en;
|
||||
|
||||
reg channel_enable;
|
||||
reg [CLOCK_DIV_WIDTH-1:0] clock_div;
|
||||
reg [CLOCK_DIV_WIDTH-1:0] div_count;
|
||||
reg amp_phase;
|
||||
reg [AMP_WIDTH-1:0] amp_out;
|
||||
|
||||
|
||||
wire fifo_wr_en;
|
||||
wire fifo_rd_en, fifo_full, fifo_empty;
|
||||
wire [AMP_WIDTH-1:0] fifo_rd_data;
|
||||
|
||||
fifo #(.ADDR_WIDTH(4), .DATA_WIDTH(16)) sample_buf(
|
||||
clk, reset,
|
||||
fifo_wr_en, fifo_rd_en,
|
||||
wr_data[AMP_WIDTH-1:0], fifo_rd_data,
|
||||
fifo_full,
|
||||
fifo_empty
|
||||
);
|
||||
|
||||
assign fifo_rd_en = (div_count == 0) && channel_enable && ~fifo_empty;
|
||||
assign fifo_wr_en = wr_en && (reg_sel == TDRAU_REG_AMP);
|
||||
|
||||
reg irq_buf, irq_enable;
|
||||
assign irq = channel_enable && irq_buf;
|
||||
|
||||
reg [DATA_WIDTH-1:0] rd_data_buf;
|
||||
assign rd_data = rd_data_buf;
|
||||
|
||||
assign amp_val = amp_out;
|
||||
assign running = channel_enable;
|
||||
|
||||
wire ctl_reg_write = wr_en && (reg_sel == TDRAU_REG_CTL);
|
||||
|
||||
/* update read data buffer */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
rd_data_buf <= {{DATA_WIDTH-8{1'b0}},
|
||||
{3{1'b0}}, irq_enable, fifo_full, fifo_empty, amp_phase, channel_enable};
|
||||
end
|
||||
|
||||
/* irq signal to interrupt controller */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
irq_buf <= 0;
|
||||
else
|
||||
if(fifo_empty && irq_enable)
|
||||
irq_buf <= 1;
|
||||
else
|
||||
irq_buf <= 0;
|
||||
end
|
||||
|
||||
/* interrupt enable flag */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
irq_enable <= 0;
|
||||
else
|
||||
if(ctl_reg_write)
|
||||
irq_enable <= wr_data[4];
|
||||
else
|
||||
if(irq_buf)
|
||||
irq_enable <= 0; // disable interrupts after an interrupt
|
||||
end
|
||||
|
||||
/* channel enable flag */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
channel_enable <= 0;
|
||||
else if (ctl_reg_write)
|
||||
channel_enable <= wr_data[0];
|
||||
end
|
||||
|
||||
/* clock divider register */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
clock_div <= 0;
|
||||
else
|
||||
if (wr_en && (reg_sel == TDRAU_REG_CLK))
|
||||
clock_div <= wr_data;
|
||||
end
|
||||
|
||||
/* divider counter */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(channel_enable)
|
||||
begin
|
||||
if(div_count == 0) // reset counter if it reaches zero
|
||||
div_count <= clock_div;
|
||||
else
|
||||
div_count <= div_count - 1; // else just decrement it
|
||||
end
|
||||
else
|
||||
if (wr_en && (reg_sel == TDRAU_REG_CLK)) // when setting divider,
|
||||
div_count <= 1; // start cycle on next clock tick
|
||||
end
|
||||
|
||||
/* amplitude out */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
amp_out <= AMP_BIAS;
|
||||
amp_phase <= 1;
|
||||
end
|
||||
else
|
||||
if (channel_enable)
|
||||
begin
|
||||
if (div_count == 0) // invert amplitude on clock tick
|
||||
begin
|
||||
amp_out <= fifo_rd_data;
|
||||
amp_phase <= ~amp_phase;
|
||||
end
|
||||
end
|
||||
else
|
||||
amp_out <= AMP_BIAS;
|
||||
|
||||
// reset phase bit when enabling the channel
|
||||
if (ctl_reg_write && wr_data[0] && ~channel_enable)
|
||||
// when channel is being enabled, phase will be flipped on next tick
|
||||
// because div_count will become zero
|
||||
amp_phase <= 1;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module tdraudio #(DATA_WIDTH=32) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire [6:0] io_addr,
|
||||
output wire [DATA_WIDTH-1:0] rd_data,
|
||||
input wire [DATA_WIDTH-1:0] wr_data,
|
||||
input wire rd_en,
|
||||
input wire wr_en,
|
||||
output wire irq_out,
|
||||
output wire pdm_out,
|
||||
output wire gain_sel,
|
||||
output wire shutdown_n
|
||||
);
|
||||
|
||||
localparam CLOCK_DIV_WIDTH = 22;
|
||||
localparam AMP_WIDTH = 16;
|
||||
localparam AMP_BIAS = 32768;
|
||||
localparam DAC_WIDTH = 18;
|
||||
|
||||
/* avoid warning about unconnected port */
|
||||
(* keep="soft" *) wire [DATA_WIDTH-1:AMP_WIDTH] _unused = wr_data[DATA_WIDTH-1:AMP_WIDTH];
|
||||
|
||||
wire [4:0] chan_sel = io_addr[6:2];
|
||||
wire [1:0] reg_sel = io_addr[1:0];
|
||||
|
||||
wire [AMP_WIDTH-1:0] amp_wr_data = wr_data[AMP_WIDTH-1:0];
|
||||
|
||||
wire [AMP_WIDTH-1:0] chan0_amp;
|
||||
wire [DATA_WIDTH-1:0] chan0_rd_data;
|
||||
wire chan0_running;
|
||||
wire chan0_irq;
|
||||
wire chan0_sel = chan_sel == 5'd0;
|
||||
wire chan0_rd_en = chan0_sel && rd_en;
|
||||
wire chan0_wr_en = chan0_sel && wr_en;
|
||||
|
||||
wire [AMP_WIDTH-1:0] chan1_amp;
|
||||
wire [DATA_WIDTH-1:0] chan1_rd_data;
|
||||
wire chan1_running;
|
||||
wire chan1_irq;
|
||||
wire chan1_sel = chan_sel == 5'd1;
|
||||
wire chan1_rd_en = chan1_sel && rd_en;
|
||||
wire chan1_wr_en = chan1_sel && wr_en;
|
||||
|
||||
wire [AMP_WIDTH-1:0] chan2_amp;
|
||||
wire [DATA_WIDTH-1:0] chan2_rd_data;
|
||||
wire chan2_running;
|
||||
wire chan2_irq;
|
||||
wire chan2_sel = chan_sel == 5'd2;
|
||||
wire chan2_rd_en = chan2_sel && rd_en;
|
||||
wire chan2_wr_en = chan2_sel && wr_en;
|
||||
|
||||
wire [AMP_WIDTH-1:0] chan3_amp;
|
||||
wire [DATA_WIDTH-1:0] chan3_rd_data;
|
||||
wire chan3_running;
|
||||
wire chan3_irq;
|
||||
wire chan3_sel = chan_sel == 5'd3;
|
||||
wire chan3_rd_en = chan3_sel && rd_en;
|
||||
wire chan3_wr_en = chan3_sel && wr_en;
|
||||
|
||||
wire running = chan0_running || chan1_running || chan2_running || chan3_running;
|
||||
|
||||
assign rd_data = chan0_sel ? chan0_rd_data :
|
||||
chan1_sel ? chan1_rd_data :
|
||||
chan2_sel ? chan2_rd_data :
|
||||
chan3_sel ? chan3_rd_data :
|
||||
{DATA_WIDTH{1'b1}};
|
||||
|
||||
wavegen chan0(clk, reset, reg_sel,
|
||||
chan0_rd_data, amp_wr_data,
|
||||
chan0_rd_en, chan0_wr_en,
|
||||
chan0_amp,
|
||||
chan0_running, chan0_irq);
|
||||
|
||||
wavegen chan1(clk, reset, reg_sel,
|
||||
chan1_rd_data, amp_wr_data,
|
||||
chan1_rd_en, chan1_wr_en,
|
||||
chan1_amp,
|
||||
chan1_running, chan1_irq);
|
||||
|
||||
wavegen chan2(clk, reset, reg_sel,
|
||||
chan2_rd_data, amp_wr_data,
|
||||
chan2_rd_en, chan2_wr_en,
|
||||
chan2_amp,
|
||||
chan2_irq, chan2_running);
|
||||
|
||||
wavegen chan3(clk, reset, reg_sel,
|
||||
chan3_rd_data, amp_wr_data,
|
||||
chan3_rd_en, chan3_wr_en,
|
||||
chan3_amp,
|
||||
chan3_running, chan3_irq);
|
||||
|
||||
reg [DAC_WIDTH:0] deltasigma_acc; // one extra bit
|
||||
wire [DAC_WIDTH:0] amp_sum = chan0_amp + chan1_amp + chan2_amp + chan3_amp; // also one overflow bit here
|
||||
assign gain_sel = 1; // gain select: 0 -> 12dB, 1 -> 6dB
|
||||
|
||||
// assign shutdown_n = running;
|
||||
assign shutdown_n = 1; /* don't enable shutdown mode, it creates a mains hum */
|
||||
|
||||
reg irq_out_buf;
|
||||
assign irq_out = irq_out_buf;
|
||||
|
||||
always @(posedge clk) irq_out_buf <= chan0_irq || chan1_irq || chan2_irq || chan3_irq;
|
||||
|
||||
/* delta-sigma DAC */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
deltasigma_acc <= 0;
|
||||
else
|
||||
// if (running)
|
||||
deltasigma_acc <= deltasigma_acc[DAC_WIDTH-1:0] + amp_sum;
|
||||
// else
|
||||
// deltasigma_acc <= deltasigma_acc[DAC_WIDTH-1:0] + (4*AMP_BIAS);
|
||||
end
|
||||
|
||||
/* 1-bit audio output */
|
||||
assign pdm_out = deltasigma_acc[DAC_WIDTH];
|
||||
endmodule
|
||||
|
|
@ -10,11 +10,13 @@
|
|||
//`define clock clk_1hz
|
||||
`define ENABLE_VGAFB
|
||||
`define ENABLE_MICROSD
|
||||
`define ENABLE_TDRAUDIO
|
||||
|
||||
module top(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire btn0,
|
||||
input wire sw0,
|
||||
input wire sw1,
|
||||
output wire led0,
|
||||
output wire led1,
|
||||
output wire led2,
|
||||
|
|
@ -58,13 +60,6 @@ module top(
|
|||
output wire sd_sck,
|
||||
input wire sd_cd
|
||||
`endif
|
||||
|
||||
`ifdef ENABLE_TDRAUDIO
|
||||
,
|
||||
output wire amp2_ain,
|
||||
output wire amp2_gain,
|
||||
output wire amp2_shutdown_n
|
||||
`endif
|
||||
);
|
||||
|
||||
reg clk_1hz;
|
||||
|
|
@ -225,44 +220,11 @@ module top(
|
|||
assign uart_tx_data = mem_write_data[7:0];
|
||||
assign uart_rd_data = { {WIDTH-10{1'b1}}, uart_rx_avail, uart_tx_busy, uart_rx_data };
|
||||
|
||||
wire audio_irq;
|
||||
|
||||
buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
|
||||
uart_baud,
|
||||
uart_txd_in, uart_rxd_out,
|
||||
uart_rx_clear, uart_tx_en,
|
||||
uart_rx_avail, uart_tx_busy,
|
||||
uart_tx_data, uart_rx_data);
|
||||
|
||||
// audio controller
|
||||
`ifdef ENABLE_TDRAUDIO
|
||||
wire [WIDTH-1:0] tdraudio_wr_data;
|
||||
wire [WIDTH-1:0] tdraudio_rd_data;
|
||||
wire tdraudio_rd_en, tdraudio_wr_en;
|
||||
wire tdraudio_irq;
|
||||
|
||||
wire tdraudio_cs_en = io_enable && (io_slot == 4);
|
||||
assign tdraudio_rd_en = tdraudio_cs_en && mem_read_enable;
|
||||
assign tdraudio_wr_en = tdraudio_cs_en && mem_write_enable;
|
||||
assign tdraudio_wr_data = mem_write_data;
|
||||
|
||||
tdraudio tdraudio0(`clock, ~rst,
|
||||
mem_addr[6:0],
|
||||
tdraudio_rd_data,
|
||||
tdraudio_wr_data,
|
||||
tdraudio_rd_en,
|
||||
tdraudio_wr_en,
|
||||
tdraudio_irq,
|
||||
amp2_ain, amp2_gain, amp2_shutdown_n);
|
||||
assign audio_irq = tdraudio_irq;
|
||||
`endif
|
||||
|
||||
// interrupt controller
|
||||
reg timer_tick;
|
||||
reg[23:0] tick_count;
|
||||
wire [2:0] irq_in = { audio_irq, timer_tick, uart_rx_avail };
|
||||
wire [2:0] irqc_rd_data0;
|
||||
wire [WIDTH-1:0] irqc_rd_data = { tick_count, 5'b0, irqc_rd_data0 };
|
||||
wire [1:0] irq_in = { timer_tick, uart_rx_avail };
|
||||
wire [1:0] irqc_rd_data0;
|
||||
wire [WIDTH-1:0] irqc_rd_data = { tick_count, 6'b0, irqc_rd_data0 };
|
||||
wire irqc_seten = mem_write_data[7];
|
||||
wire irqc_cs = io_enable && (io_slot == 3);
|
||||
|
||||
|
|
@ -274,11 +236,16 @@ module top(
|
|||
(io_slot == 2) ? fb_rd_data :
|
||||
`endif
|
||||
(io_slot == 3) ? irqc_rd_data:
|
||||
`ifdef ENABLE_TDRAUDIO
|
||||
(io_slot == 4) ? tdraudio_rd_data:
|
||||
`endif
|
||||
|
||||
-1;
|
||||
|
||||
buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
|
||||
uart_baud,
|
||||
uart_txd_in, uart_rxd_out,
|
||||
uart_rx_clear, uart_tx_en,
|
||||
uart_rx_avail, uart_tx_busy,
|
||||
uart_tx_data, uart_rx_data);
|
||||
|
||||
// CPU -----------------------------------------------------------------
|
||||
stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
|
||||
.addr(mem_addr),
|
||||
|
|
@ -286,7 +253,7 @@ module top(
|
|||
.read_ins(dram_read_ins),
|
||||
.data_out(mem_write_data), .write_enable(mem_write_enable),
|
||||
.mem_wait(mem_wait),
|
||||
.debug1(led1), .debug2(led2), .debug3(led3));
|
||||
.led1(led1), .led2(led2), .led3(led3));
|
||||
|
||||
// Interrupt Controller
|
||||
irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@
|
|||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/stack.v" Mode="RelativeOnly">
|
||||
<File Path="$PSRCDIR/stack.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
|
|
@ -142,7 +142,7 @@
|
|||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/testbench.v"/>
|
||||
<File Path="$PPRDIR/rom.mem" Mode="RelativeOnly">
|
||||
<File Path="$PPRDIR/rom.mem">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
|
|
@ -173,14 +173,14 @@
|
|||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/bram_tdp.v" Mode="RelativeOnly">
|
||||
<File Path="$PSRCDIR/bram_tdp.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/palette.v" Mode="RelativeOnly">
|
||||
<File Path="$PSRCDIR/palette.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
|
|
@ -205,13 +205,6 @@
|
|||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/tdraudio.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top"/>
|
||||
|
|
@ -356,12 +349,17 @@
|
|||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
<StratHandle Name="Flow_PerfOptimized_high" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design">
|
||||
<Option Id="Directive">7</Option>
|
||||
<Option Id="FsmExtraction">1</Option>
|
||||
<Option Id="KeepEquivalentRegisters">1</Option>
|
||||
<Option Id="NoCombineLuts">1</Option>
|
||||
<Option Id="ResourceSharing">2</Option>
|
||||
<Option Id="ShregMinSize">5</Option>
|
||||
</Step>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
|
|
@ -380,9 +378,7 @@
|
|||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
|
|
|||
149
utils/serload.py
149
utils/serload.py
|
|
@ -16,7 +16,6 @@
|
|||
# limitations under the License.
|
||||
|
||||
import sys
|
||||
import os
|
||||
import serial
|
||||
import time
|
||||
import random
|
||||
|
|
@ -42,6 +41,30 @@ def get_default_device():
|
|||
return '/dev/ttyUSB1'
|
||||
|
||||
|
||||
def serwrite_slow(databytes, ser):
|
||||
total = len(data)
|
||||
count = 1
|
||||
for d in data:
|
||||
sys.stdout.write("writing {0:02x} {1:04d}/{2:04d}\r".format(ord(d), count, total))
|
||||
ser.write(bytes(d,"utf8"))
|
||||
count += 1
|
||||
time.sleep(0.020)
|
||||
print()
|
||||
|
||||
|
||||
def serwrite(datafile, ser):
|
||||
with open(datafile) as f:
|
||||
data = f.read()
|
||||
total = len(data)
|
||||
count = 1
|
||||
for d in data:
|
||||
sys.stdout.write("writing {0:02x} {1:04d}/{2:04d}\r".format(ord(d), count, total))
|
||||
ser.write(bytes(d,"utf8"))
|
||||
count += 1
|
||||
time.sleep(0.020)
|
||||
print()
|
||||
|
||||
|
||||
def checksum(databytes):
|
||||
i = 0
|
||||
cksum = 0
|
||||
|
|
@ -62,29 +85,13 @@ def sendchar(char, ser):
|
|||
ser.write(char.to_bytes(1, 'big'))
|
||||
|
||||
|
||||
def sendcommand(ser, cmd=b'L', verbose=False):
|
||||
verbose = True
|
||||
def sendcommand(ser, cmd=b'L'):
|
||||
ser.write(cmd)
|
||||
resp = ser.read_until()
|
||||
if verbose:
|
||||
print(cmd,"sent, response:", str(resp))
|
||||
return resp
|
||||
|
||||
|
||||
# send command and wait for echo
|
||||
def commandwait(ser, cmd):
|
||||
resp = sendcommand(ser, cmd, verbose=False)
|
||||
if len(resp) == 0:
|
||||
print("timeout sending '{}' command".format(cmd))
|
||||
return None
|
||||
|
||||
if resp != bytearray(cmd + b"\r\n"):
|
||||
print("invalid response to '{}' command".format(cmd))
|
||||
return None
|
||||
|
||||
return resp
|
||||
|
||||
|
||||
def send_size_header(ser, filesize):
|
||||
ser.write(b'\x05') # ENQ
|
||||
resp = ser.read(1)
|
||||
|
|
@ -146,8 +153,6 @@ def serload_bin(datafile, ser):
|
|||
|
||||
data += bytearray(pad)
|
||||
|
||||
print("{} total blocks".format((len(data) + blocksize - 1) // blocksize))
|
||||
|
||||
if not send_size_header(ser, filesize):
|
||||
print("Error sending size header.")
|
||||
return
|
||||
|
|
@ -274,8 +279,18 @@ def serdownload(fname, ser):
|
|||
|
||||
def mput(filenames, ser):
|
||||
for f in filenames:
|
||||
resp = set_filename(f, ser)
|
||||
if resp is None:
|
||||
f_encoded = f.encode('utf8')
|
||||
print("Setting filename", f)
|
||||
resp = sendcommand(ser, b'S')
|
||||
if len(resp) == 0:
|
||||
print("timeout sending 'S' command")
|
||||
return
|
||||
if resp != b'S\r\n' and resp != b'> S\r\n':
|
||||
print("unrecognized response to 'S' command, aborting")
|
||||
return
|
||||
resp = sendcommand(ser, f_encoded + b'\r')
|
||||
if not f_encoded in resp:
|
||||
print("unrecognized response to filename, aborting")
|
||||
return
|
||||
serload_bin(f, ser)
|
||||
|
||||
|
|
@ -284,92 +299,12 @@ def mput(filenames, ser):
|
|||
time.sleep(2)
|
||||
|
||||
|
||||
def set_filename(f, ser):
|
||||
f_encoded = f.encode('utf8')
|
||||
print("Setting filename", f)
|
||||
resp = commandwait(ser, b'S')
|
||||
if resp is None:
|
||||
return None
|
||||
resp = sendcommand(ser, f_encoded + b'\r')
|
||||
if not f_encoded in resp:
|
||||
print("unrecognized response to filename, aborting")
|
||||
return None
|
||||
return resp
|
||||
|
||||
|
||||
def getnamedfile(filename, ser):
|
||||
resp = set_filename(filename, ser)
|
||||
if resp is None:
|
||||
return None
|
||||
serdownload(filename, ser)
|
||||
|
||||
|
||||
def putnamedfile(filename, ser):
|
||||
resp = set_filename(filename, ser)
|
||||
if resp is None:
|
||||
return None
|
||||
serload_bin(filename, ser)
|
||||
print("Remote status:")
|
||||
showdata(ser)
|
||||
|
||||
|
||||
def showdata(ser):
|
||||
|
||||
promptseen = False
|
||||
|
||||
while not promptseen:
|
||||
c = ser.read(1)
|
||||
if c == b'>':
|
||||
promptseen = True
|
||||
else:
|
||||
print(c.decode('utf8'), end='')
|
||||
rest = ser.read(1)
|
||||
|
||||
|
||||
def localdir():
|
||||
result = os.walk(".")
|
||||
for dirpath, dirnames, filenames in os.walk("."):
|
||||
for f in filenames:
|
||||
print(f)
|
||||
break
|
||||
|
||||
|
||||
def interactive(ser):
|
||||
done = False
|
||||
while not done:
|
||||
args = input("> ").strip().split()
|
||||
if len(args) > 0:
|
||||
cmd = args[0]
|
||||
args.pop(0)
|
||||
if cmd == 'dir':
|
||||
if commandwait(ser, b'Y') is None:
|
||||
return
|
||||
showdata(ser)
|
||||
elif cmd == 'get':
|
||||
if len(args) > 1:
|
||||
print("exactly one argument required (filename)")
|
||||
else:
|
||||
getnamedfile(args[0], ser)
|
||||
elif cmd == 'put':
|
||||
if len(args) > 1:
|
||||
print("exactly one argument required (filename)")
|
||||
else:
|
||||
putnamedfile(args[0], ser)
|
||||
elif cmd == 'ldir':
|
||||
if len(args) > 0:
|
||||
print("superfluous argument")
|
||||
else:
|
||||
localdir()
|
||||
else:
|
||||
print("Unknown command. Valid commands are: dir get ldir put")
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
argparser = argparse.ArgumentParser(
|
||||
description='transfer files from/to the Tridora-CPU')
|
||||
argparser.add_argument('-d', '--device', help='serial device', default=get_default_device())
|
||||
argparser.add_argument('command', choices=['get', 'put', 'mput', 'interactive'])
|
||||
argparser.add_argument('filename', nargs='*')
|
||||
argparser.add_argument('command', choices=['get', 'put', 'mput'])
|
||||
argparser.add_argument('filename', nargs='+')
|
||||
args = argparser.parse_args()
|
||||
|
||||
cmd = args.command
|
||||
|
|
@ -384,10 +319,8 @@ if __name__ == "__main__":
|
|||
serload_bin(filenames[0], ser)
|
||||
elif cmd == 'mput':
|
||||
mput(filenames, ser)
|
||||
elif cmd == 'interactive':
|
||||
interactive(ser)
|
||||
else:
|
||||
print("should not get here")
|
||||
|
||||
#if cmd is not None:
|
||||
# ser.close()
|
||||
if cmd is not None:
|
||||
ser.close()
|
||||
|
|
|
|||
|
|
@ -538,9 +538,6 @@ def create_image_with_stuff(imgfile):
|
|||
slotnr = putfile("../progs/recover.prog", None , f, part, partstart, slotnr)
|
||||
slotnr = putfile("../progs/changemem.prog", None , f, part, partstart, slotnr)
|
||||
|
||||
slotnr = putfile("../lib/pcmaudio.s", None , f, part, partstart, slotnr)
|
||||
slotnr = putfile("../lib/pcmaudio.inc", None , f, part, partstart, slotnr)
|
||||
|
||||
listdir(f, part)
|
||||
|
||||
# third partition
|
||||
|
|
@ -603,8 +600,6 @@ def create_image_with_stuff(imgfile):
|
|||
|
||||
slotnr = putfile("../examples/lines.pas", None , f, part, partstart, slotnr)
|
||||
|
||||
slotnr = putfile("../examples/pcmtest2.pas", None , f, part, partstart, slotnr)
|
||||
|
||||
slotnr = putfile("../examples/pictviewer.pas", None , f, part, partstart, slotnr)
|
||||
slotnr = putfile("../examples/Toco_Toucan.pict", None , f, part, partstart, slotnr)
|
||||
slotnr = putfile("../examples/shinkansen.pict", None , f, part, partstart, slotnr)
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
import sys
|
||||
import random, struct
|
||||
import wave
|
||||
|
||||
freq = 16000
|
||||
BIAS = 32768
|
||||
def convert(srcpath, destpath):
|
||||
outdata = bytearray()
|
||||
with wave.open(srcpath, mode="rb") as f:
|
||||
params = f.getparams()
|
||||
print(params.nchannels, params.sampwidth, params.framerate)
|
||||
|
||||
frames = f.readframes(2*1024*1024)
|
||||
for i in range(0, len(frames), 2):
|
||||
v = int.from_bytes(frames[i:i+2], "little", signed=True)
|
||||
v += BIAS
|
||||
hi = (v & 0xFF00) >> 8
|
||||
lo = (v & 0x00FF)
|
||||
outdata.append(hi)
|
||||
outdata.append(lo)
|
||||
|
||||
with open(destpath, mode="wb") as f:
|
||||
f.write(outdata)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sourcefilename = sys.argv[1]
|
||||
destfilename = sys.argv[2]
|
||||
convert(sourcefilename, destfilename)
|
||||
Loading…
Add table
Add a link
Reference in a new issue