7 commits

Author	SHA1	Message	Date
slederer	7cc9ee807d	tdraudio: remove pulse/noise waves, add sample buffer and irq	2025-10-04 00:09:10 +02:00
slederer	c354bb8cb8	tdraudio: implement multiple channels	2025-09-26 01:36:26 +02:00
slederer	d5888861d3	tdraudio: first step of implementing a sound generator	2025-09-23 23:39:04 +02:00
slederer	8abd9fc126	tridoracpu: cache bug fixes	2025-03-29 01:29:16 +01:00
slederer	b6bd487b7e	tridoracpu: first attempt at instruction cache	2025-03-16 00:10:53 +01:00
slederer	c2d7c6627a	tridoracpu: reduce clock speed, fix vblank flag in vgafb	2025-03-13 22:37:56 +01:00
slederer	a441e7e042	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00

Renamed from rtl/src/top.v (Browse further)