slederer/Tridora-CPU
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59 commits 7 branches 2 tags 8.7 MiB
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3 commits

Author SHA1 Message Date
slederer
ac42eec912 tridoracpu: add missing xci file for the DRAM controller 2025-03-09 23:51:22 +01:00
slederer
4f504c0f48 stdlib: start with valid random seed; other small changes 
-  tridoracpu: fix comment
-  add benchmark some results
 2025-03-09 01:57:11 +01:00
slederer
a441e7e042 import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00