3 commits

Author	SHA1	Message	Date
slederer	a9412d1339	tdraudio: fix wiring for channel 2, irqctrl: increase delay	2026-01-01 02:07:36 +01:00
slederer	7cc9ee807d	tdraudio: remove pulse/noise waves, add sample buffer and irq	2025-10-04 00:09:10 +02:00
slederer	a441e7e042	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00

Renamed from rtl/src/irqctrl.v (Browse further)