2 commits

Author	SHA1	Message	Date
slederer	c2d7c6627a	tridoracpu: reduce clock speed, fix vblank flag in vgafb	2025-03-13 22:37:56 +01:00
slederer	a441e7e042	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00

Renamed from rtl/arty-a7/Arty-A7-35-Master.xdc (Browse further)