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tdraudio: correctly generate silence, clear DAC accumulator

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slederer 2025-09-30 00:50:33 +02:00
parent 4d4cc0c535
commit e690d3eb2b
2 changed files with 25 additions and 15 deletions
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12
tridoracpu/tridoracpu.xpr
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@ -378,10 +378,10 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. low setting, least pessimistic)" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Uses multiple algorithms for optimization, placement, and routing to get potentially better results." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Performance_NetDelay_low" Flow="Vivado Implementation 2024">
<Desc>To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. low setting, least pessimistic)</Desc>
<StratHandle Name="Performance_Explore" Flow="Vivado Implementation 2024">
<Desc>Uses multiple algorithms for optimization, placement, and routing to get potentially better results.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design">
@ -389,14 +389,14 @@
</Step>
<Step Id="power_opt_design"/>
<Step Id="place_design">
<Option Id="Directive">3</Option>
<Option Id="Directive">0</Option>
</Step>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design">
<Option Id="Directive">2</Option>
<Option Id="Directive">0</Option>
</Step>
<Step Id="route_design">
<Option Id="Directive">1</Option>
<Option Id="Directive">0</Option>
</Step>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream">