tdraudio: first step of implementing a sound generator
This commit is contained in:
parent
f79d7d622a
commit
d5888861d3
4 changed files with 119 additions and 8 deletions
74
tridoracpu/tridoracpu.srcs/tdraudio.v
Normal file
74
tridoracpu/tridoracpu.srcs/tdraudio.v
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module tdraudio #(DATA_WIDTH=32) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire [3:0] reg_sel,
|
||||
output wire [DATA_WIDTH-1:0] rd_data,
|
||||
input wire [DATA_WIDTH-1:0] wr_data,
|
||||
input wire rd_en,
|
||||
input wire wr_en,
|
||||
|
||||
output wire pdm_out,
|
||||
output wire gain_en,
|
||||
output wire shutdown_n
|
||||
);
|
||||
|
||||
localparam CLOCK_DIV_WIDTH = 22;
|
||||
|
||||
localparam TDRAU_REG_CTL = 0; /* control register */
|
||||
localparam TDRAU_REG_CLK = 1; /* clock divider register */
|
||||
|
||||
reg audio_out;
|
||||
reg channel_enable;
|
||||
reg [CLOCK_DIV_WIDTH-1:0] clock_div;
|
||||
reg [CLOCK_DIV_WIDTH-1:0] div_count;
|
||||
|
||||
assign pdm_out = audio_out;
|
||||
assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
|
||||
assign gain_en = 0;
|
||||
assign shutdown_n = channel_enable;
|
||||
|
||||
/* channel enable flag */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
channel_enable <= 0;
|
||||
else if (wr_en && (reg_sel == TDRAU_REG_CTL))
|
||||
channel_enable <= wr_data[0];
|
||||
end
|
||||
|
||||
/* clock divider register */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
clock_div <= 0;
|
||||
else if (wr_en && (reg_sel == TDRAU_REG_CLK))
|
||||
clock_div <= wr_data;
|
||||
end
|
||||
|
||||
/* divider counter */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(channel_enable)
|
||||
begin
|
||||
if(div_count == 0) // reset counter if it reaches zero
|
||||
div_count <= clock_div;
|
||||
else
|
||||
div_count <= div_count - 1; // else just decrement it
|
||||
end
|
||||
else
|
||||
if (wr_en && (reg_sel == TDRAU_REG_CLK))
|
||||
div_count <= 0; // set counter to zero whenever the clock divider is set
|
||||
end
|
||||
|
||||
/* 1-bit audio output */
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (reset)
|
||||
audio_out <= 0;
|
||||
else
|
||||
if (channel_enable && (div_count == 0))
|
||||
audio_out <= ~audio_out;
|
||||
end
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue