slederer/Tridora-CPU
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages 3 Wiki Activity Actions

mem: make SRAM size configurable

Browse source
This commit is contained in:
slederer 2025-09-09 00:13:56 +02:00
parent 52f82fe6ae
commit d2cae9480c
2 changed files with 11 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

8
tridoracpu/tridoracpu.srcs/mem.v
View file

@ -91,8 +91,10 @@ module mem #(parameter ADDR_WIDTH = 32,
// RAM1 $1000 - $FFFF 60K
// RAM2 $10000 - $FFFFFFFF ~4GB
localparam RAM1_ADDR_WIDTH = 16;
wire ram_cs = addr[ADDR_WIDTH-1:12] != { {(ADDR_WIDTH-12){1'b0}}};
wire ram1_cs = ram_cs && (addr[ADDR_WIDTH-1:16] == { {(ADDR_WIDTH-16){1'b0}}});
wire ram1_cs = ram_cs && (addr[ADDR_WIDTH-1:RAM1_ADDR_WIDTH] == { {(ADDR_WIDTH-RAM1_ADDR_WIDTH){1'b0}}});
wire ram2_cs = ram_cs && !ram1_cs;
wire rom_cs = !ram_cs && addr[11] == 1'b0;
wire io_cs = !ram_cs && addr[11] == 1'b1;
@ -116,10 +118,10 @@ module mem #(parameter ADDR_WIDTH = 32,
// test
reg [1:0] wait_state;
ram32 #(.ADDR_WIDTH(16)) ram0 // 64KB RAM
ram32 #(.ADDR_WIDTH(RAM1_ADDR_WIDTH)) ram0 // 64KB RAM
(
.clk(clk),
.addr(addr[15:0]),
.addr(addr[RAM1_ADDR_WIDTH-1:0]),
.data_out(ram_out),
.read_enable(ram_read),
.data_in(data_in),